External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 3/28/2022

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Document Table of Contents Per-interface Parameter Table Structure

The Per-Interface parameter table’s base address is equal to: (user-ram base address) + (interface parameter table offset, read from gpt_INTERFACE_PAR_PTRS array).
Table 174.  Per-interface Parameters
Address Data Type Bit Position Field Name Description
base address for per-interface parameter table (per_interface_base_address) = 0x0500_0000 + per-interface offset alt_u16  Bit[15:0]  pt_IP_VER

IP ACDS version encoded as a 16-bit value, where:

  • Bit 15 is reserved.
  • Bits 14-10 encode the major release number.
  • Bits 9-6 encode the minor release number.
  • Bits 5-3 encode the service pack number.
  • Bits 2-0 encode whether this is a special variant.
alt_u16 Bit[31:16] pt_INTERFACE_PAR_VER  Version of this parameter table ( Nios® checks compatibility).
per_interface_base_address + 0x04  alt_u16 Bit[15:0] pt_DEBUG_DATA_PTR  Debug_data_struct offset from the starting address of the user-ram.
alt_u16 Bit[31:16] pt_UNUSED Unused.
per_interface_base_address + 0x08 alt_u8 Bit[7:0]  pt_MEMORY_TYPE  Memory type, defined by ENUM_MEM_TYPE.
alt_u8 Bit[15:8] pt_DIMM_TYPE  DIMM type, defined by ENUM_DIMM_TYPE.
alt_u8 Bit[31:16] pt_RESERVED  Reserved entry.
per_interface_base_address + 0x0C  alt_u32 Bit[31:0]   pt_AFI_CLK_FREQ_KHZ  AFI clock frequency in KHz.
per_interface_base_address + 0x10  alt_u8 Bit[7:0]  pt_BURST_LEN  Burst length.
alt_u8 Bit[15:8] pt_READ_LATENCY 

Effective Read Latency. The value is a fixed-point number in 7.1 format: bit [6:0] is the integer part and bit 7 is the fractional part.

For example:

  • value 0x2 means RL=2
  • value 0x82 means RL=2.5 (useful for QDR memory)

The value should be equal to (CL + AL + PL), where:

CL is CAS Latency, AL is Additive Latency (for the memories supporting it; 0 otherwise), and PL is Parity Latency (for memories supporting it if parity feature is enabled; 0 otherwise).

alt_u8 Bit[23:16] pt_WRITE_LATENCY  Effective Write Latency. Equals (WL + AL + PL), where:

WL is Write Latency, and AL and PL are the same as those used in READ_LATENCY above.

alt_u8 Bit[31:24]  pt_NUM_RANKS  Number of electrical loads of DQ/DQS.
per_interface_base_address + 0x14  alt_u8   Bit[7:0]  pt_NUM_DIMMS  Number of DIMM slots.
alt_u8   Bit[15:8]  pt_NUM_DQS_WR  Number of write DQS pins.
alt_u8   Bit[23:16] pt_NUM_DQS_RD  Number of read DQS pins.
alt_u8   Bit[31:24] pt_NUM_DQ  Number of DQ pins.
per_interface_base_address + 0x18  alt_u8   Bit[7:0]  pt_NUM_DM  Number of DM pins (or DM/DBI pins for DDR4).
alt_u8   Bit[15:8] pt_ADDR_WIDTH  Number of address pins.
alt_u8   Bit[23:16] pt_BANK_WIDTH  Bank Address width; equals log2(number-of-banks).
alt_u8   Bit[31:24] pt_CS_WIDTH  CS width; in most cases equals NUM_RANKS.
per_interface_base_address + 0x1C  alt_u8   Bit[7:0]  pt_CKE_WIDTH  CKE width; in most cases equals CS_WIDTH.
alt_u8   Bit[15:8] pt_ODT_WIDTH  ODT width; in most cases equals CS_WIDTH.
alt_u8   Bit[23:16]  pt_C_WIDTH  Chip ID width for DDR4.
alt_u8   Bit[31:24]  pt_BANK_GROUP_WIDTH  Bank group width for DDR4.
per_interface_base_address + 0x20  alt_u8  Bit[7:0]  pt_ADDR_MIRROR Address mirroring configuration; one bit enable per rank enables.
alt_u8  Bit[15:8]  pt_CK_WIDTH  Number of pairs of CK/CK_N; in most cases equals to CS_WIDTH.
alt_u8  Bit[23:16]  pt_CAL_DATA_SIZE  Size of the pt_CAL_DATA_PTR array (in bytes).
alt_u8  Bit[31:24]  pt_NUM_LRDIMM_CFG  (LRDIMM only) Number of the triplets of code words for LRDIMM. On non-LRDIMM configuration this entry should be set to 0.
per_interface_base_address + 0x24  alt_u8  Bit[7:0]  pt_NUM_AC_ROM_ENUMS  Number of AC ROM enums for the current protocol.
alt_u8  Bit[15:8] pt_NUM_CENTERS  Number of tiles used by this interface.
alt_u8  Bit[23:16] pt_NUM_CA_LANES  Number of command/address lanes.
alt_u8  Bit[31:24] pt_NUM_DATA_LANES  Number of data lanes.
per_interface_base_address + 0x28  alt_u32  Bit[31:0]  pt_ODT_TABLE_LO  ODT table; 4 bits as in ENUM_ODT_TABLE order: [odt3_cs1, odt2_cs1, ..., odt0_cs0]
per_interface_base_address + 0x2C  alt_u32  Bit[31:0]   pt_ODT_TABLE_HI  ODT table; 4 bits as in ENUM_ODT_TABLE order: [odt3_cs3, odt2_cs3, ..., odt0_cs2]
per_interface_base_address + 0x34  alt_u16 Bit[15:0]  pt_RESERVED Field not used currently.
alt_u16 Bit[31:16]   pt_CAL_DATA_PTR  cal_data array offset from the starting address of the user-ram. This array's structure is described in the Parameter Table Arrays section.
per_interface_base_address + 0x38  alt_u32 Bit[31:0]  pt_DBG_SKIP_RANKS  Each set bit indicates that storing calibration report information for the corresponding rank should be skipped. For example, if bit[1]==1, then in a 2-rank design, the second rank's calibration debug information is not stored.
per_interface_base_address + 0x3C  alt_u32 Bit[31:0] pt_DBG_SKIP_GROUPS  Each set bit indicates that storing calibration report information for the corresponding DQS group should be skipped.
per_interface_base_address + 0x40  alt_u32 Bit[31:0]  pt_DBG_SKIP_STEPS  Each set bit represents a calibration step which should be skipped, as defined in ENUM_DBG_CALIB_SKIP.
per_interface_base_address + 0x44  alt_u8 Bit[7:0]  pt_NUM_MR  Number of words that store values to be written to Mode Registers.
alt_u8 Bit[15:8]  pt_NUM_DIMM_MR  Number of words that store control words for DIMM.
alt_u16 Bit[31:16]  pt_TILE_ID_PTR  tile_id array pointer, as an offset from the starting address of the user-ram; This array maps IDs of lanes used by the memory interface to the tiles they are placed in.
per_interface_base_address + 0x48  alt_u16 Bit[15:0]  pt_PIN_ADDR_PTR  pin_addr array pointer, as an offset from the starting address of the user-ram; This array stores the pin locations (on the calbus) of command/address and data pins.
alt_u16 Bit[31:16]  pt_MR_PTR  Mode Register and RDIMM/LRDIMM control word array pointer, as an offset from the starting address of the user RAM.

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