Any I/O banks that do not support transceiver operations in Intel® Agilex™ FPGAs support external memory interfaces. However, DQS (data strobe or data clock) and DQ (data) pins are listed in the device pin tables and are fixed at specific locations in the device. You must adhere to these pin locations to optimize routing, minimize skew, and maximize margins. Always check the pin table for the actual locations of the DQS and DQ pins.
You can find the pin tables at the following location: https://www.intel.com/content/www/us/en/programmable/support/literature/lit-dp.html.
Note: Maximum interface width varies from device to device depending on the number of I/O pins and DQS or DQ groups available. Achievable interface width also depends on the number of address and command pins that the design requires. To ensure adequate PLL, clock, and device routing resources are available, you should always test fit any IP in the Intel® Quartus® Prime Prime software before PCB sign-off.
Intel® devices do not limit the width of external memory interfaces beyond the following requirements:
- Maximum possible interface width in any particular device is limited by the number of DQS groups available.
- Sufficient clock networks are available to the interface PLL as required by the IP.
- Sufficient spare pins exist within the chosen bank or side of the device to include all other address and command, and clock pin placement requirements.
Note: The greater the number of banks, the greater the skew, hence Intel® recommends that you always generate a test project of your desired configuration and confirm that it meets timing.