External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 3/28/2022
Public

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9.6. IP-Supplied Parameters that You Might Need to Override

The IP generation framework automatically creates parameters to designate the number of ranks and the number of components in the address/command channel. However, there are situations where the IP framework is not aware of modifications that are made on your PCB — for example, repeater or buffer devices, additional external termination resistors, or non-standard memory components.

In these cases, it may be necessary for you to modify these generated parameters. The table below highlights some of the parameters that you might need to change to create a customized simulation deck.

Table 151.  
Parameter Name Description Reasons for Modification
MEM_VCC Specifies the memory voltage. This is set to 1.2V for DDR4 and QDR4 applications by default. This value may be raised or lowered to account for regulator tolerances or PCB PDN IR droop.
MEMCLK_COMP_IBIS Specifies the IBIS model name for the clock input buffer on the memory model. This value may need to change if a different memory model or a buffer device is used.
MEMAC_IBIS Specifies the IBIS model name for the address/command input buffers on the memory model. This value may need to change if a different memory model or a buffer device is used.
MEMAC_RANKS Specifies the number of address/command ranks in the system. This value may need to change if the number of address/command loads differs from this value due to the use of buffer devices or multi-die components.
MEMAC_COMPS_PER_RANK Specifies the number of address/command components on the flyby chain. This value may need to change if non-standard memory devices are used and the number of components in the chain differs from this value, or if a buffer chip is used.
MEM_DQ_RANKS Specifies the number of data ranks in the system. This value may need to change if the number of databus ranks differs from this value.
WR_MEM_*_IBIS Specifies the name of the IBIS model on the memory to be used during write operations. These values may need to be changed if the naming of the IBIS models supplied by the vendor does not align to this format.
RD_MEM_*_IBIS Specifies the name of the IBIS model on the memory to be used during read operations. These values may need to be changed if the naming of the IBIS models supplied by the vendor does not align to this format.
AC_M_*_IBISTYPE Specifies the type of IBIS buffer used by the memory model for address/command pins. Address/command pins usually use the IBIS model type of “input” (buffer type = 1), but this may differ across vendor models.
DQ_WR_M_*_IBISTYPE Specifies the type of IBIS buffer used by the memory model for DQ pins in read mode (FPGA write operations). DQ pins in read mode usually use the IBIS model type of “input” (buffer type = 1), but this may differ across vendor models.
DQ_RD_M_*_IBISTYPE Specifies the type of IBIS buffer used by the memory model for DQ pins in write mode (FPGA read operations). DQ pins in write mode usually use the IBIS model type of “input_output” (buffer type = 3), but this may differ across vendor models.
Table 152.  Customizable IP-Generated SPICE Parameters
Parameter Name Description
MEM_VCC Specifies the memory voltage. This is set to 1.2V for DDR4 and QDR4 applications.
MEMCLK_COMP_IBIS Specifies the IBIS model name for the clock input buffer on the memory model. You may need to change this value if a different memory model or a buffer device is used.
MEMAC_IBIS Specifies the IBIS model name for the address/command input buffers on the memory model. You may need to change this value if a different memory model or a buffer device is used.
MEMAC_RANKS Specifies the number of address/command ranks in the system. You may need to change this value if the number of address/command loads differs from this value due to the use of buffer devices.
MEMAC_COMPS_PER_RANK Specifies the number of address/command components on the fly-by chain. You may need to change this value if non-standard memory devices are used and the number of components in the chain differs from this value, or if a buffer chip is used.
MEM_DQ_RANKS Specifies the number of data ranks in the system. You may need to change this value if the number of databus ranks differs from this value.
WR_MEM_*_IBIS Specifies the name of the IBIS model on the memory to be used during write operations. You may need to change these values if the naming of the IBIS models supplied by the vendor does not align to this format.
RD_MEM_*_IBIS Specifies the name of the IBIS model on the memory to be used during read operations. You may need to change these values if the naming of the IBIS models supplied by the vendor does not align to this format.
AC_M_*_IBISTYPE Specifies the type of IBIS buffer used by the memory model for address/command pins. Normally, address/command pins use the IBIS model type of input (buffer type = 1), but this may differ across vendor models.
DQ_WR_M_*_IBISTYPE Specifies the type of IBIS buffer used by the memory model for DQ pins in read mode (FPGA write operations). Normally, DQ pins in read mode use the IBIS model type of input (buffer type = 1), but this may differ across vendor models.
DQ_RD_M_*_IBISTYPE Specifies the type of IBIS buffer used by the memory model for DQ pins in write mode (FPGA read operations). Normally, DQ pins in write mode use the IBIS model type of input_output (buffer type = 3), but this may differ across vendor models.

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