External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 3/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.1.2.6. mem for QDR-IV

Interface between FPGA and external memory
Table 45.  Interface: memInterface type: Conduit
Port Name Direction Description
mem_ck Output CK clock
mem_ck_n Output CK clock (negative leg)
mem_dka Output DK clock for port A
mem_dka_n Output DK clock for port A (negative leg)
mem_dkb Output DK clock for port B
mem_dkb_n Output DK clock for port B (negative leg)
mem_a Output Address
mem_reset_n Output Asynchronous reset
mem_lda_n Output Synchronous load for port A
mem_ldb_n Output Synchronous load for port B
mem_rwa_n Output Synchronous read/write for port A
mem_rwb_n Output Synchronous read/write for port B
mem_lbk0_n Output Loopback mode
mem_lbk1_n Output Loopback mode
mem_cfg_n Output Configuration bit
mem_ap Output Address parity
mem_ainv Output Address inversion
mem_dqa Bidirectional Read/write data for port A
mem_dqb Bidirectional Read/write data for port B
mem_dinva Bidirectional Read/write data inversion for port A
mem_dinvb Bidirectional Read/write data inversion for port B
mem_qka Input Read data clock for port A
mem_qka_n Input Read data clock for port A (negative leg)
mem_qkb Input Read data clock for port B
mem_qkb_n Input Read data clock for port B (negative leg)
mem_pe_n Input Address parity error flag

Did you find the information on this page useful?

Characters remaining:

Feedback Message