External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 3/28/2022

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4.4.29. ecc6: Address of Most Recent Correction Command Dropped

address=146(32 bit)

Field Bit High Bit Low Description Access
sts_corr_dropped_addr 31 0 Address of the most recent correction command dropped. Read

About ECC Errors in DDR3 and DDR4 Interfaces

ECC errors are categorized as either single-bit errors (which are correctable by ECC code), or double-bit errors (which are not correctable). You can determine whether an ECC error has occurred, by checking the values of the ecc4 register fields sts_ecc_intr, sts_sbe_error, and sts_dbe_error.

  • If a double-bit error has occurred, it indicates that the memory is corrupted and cannot be corrected by ECC code. You can choose to reboot your system.
  • If a single-bit error has occurred, the controller attempts to correct the error by performing a write-back to memory using the fixed data plus an ECC code. The write-back is enabled when you have selected Enable Auto Error Correction to External Memory on the Controller tab in the IP parameter. The write-back requires space in the command queue and in the data FIFO buffer; because Intel® Agilex™ FPGAs have only 16 command queues, it is possible that the controller may not be able to schedule the write-back, in which case the write-back may be dropped. You can determine whether a write-back has been dropped, by reading the status of the ecc4 register fields ctrl_ecc_sts_corr_dropped_count, ctrl_ecc_sts_corr_dropped_addr, ctrl_ecc_sts_corr_dropped, and ctrl_ecc_sts_intr registers.

    If you discover that a write-back has been dropped, you can do either of two things:

    • You can ignore the dropped write-back, because it is a single-bit error that the controller may be able to detect and correct on the next memory read without any intervention – provided the condition does not further deteriorate into a double-bit error.
    • You can read the address from the ecc6 register field ctrl_ecc_sts_corr_dropped_addr, and perform a memory write with byte_enable=0, thereby causing the controller to access the memory location again and schedule a new write-back.

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