External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 3/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.1.1. Intel® Agilex™ EMIF Architecture: I/O Subsystem

In Intel® Agilex™ devices, the I/O subsystem consists of two rows at the edge of the core.

The I/O subsystem provides the following features:

  • General-purpose I/O registers and I/O buffers
  • On-chip termination control (OCT)
  • I/O PLLs
    • I/O Bank I/O PLL for external memory interfaces and user logic
    • Fabric-feeding for non-EMIF/non-LVDS SERDES IP applications
  • True Differential Signaling
  • External memory interface components, as follows:
    • Hard memory controller
    • Hard PHY
    • Hard Nios processor and calibration logic
    • DLL
Figure 2.  Intel® Agilex™ I/O Subsystem

The following figure depicts the I/O subsystem structure for AGF014/AGF012 series devices. I/O banks 2B and 3B are the locations of calibration I/O SSMs in these devices.

Did you find the information on this page useful?

Characters remaining:

Feedback Message