External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 3/28/2022
Public

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3.6. Intel® Agilex™ EMIF for Hard Processor Subsystem

The Intel® Agilex™ EMIF IP can enable the Intel® Agilex™ Hard Processor Subsystem (HPS) to access external DRAM memory devices.

To enable connectivity between the Intel® Agilex™ HPS and the Intel® Agilex™ EMIF IP, you must create and configure an instance of the Intel® Agilex™ External Memory Interface for HPS IP core, and use Platform Designer to connect it to the Intel® Agilex™ Hard Processor Subsystem instance in your system.

Supported Modes

The Intel® Agilex™ Hard Processor Subsystem is compatible with the following external memory configurations:

Table 12.   Intel® Agilex™ Hard Processor Subsystem Compatibility
Protocol DDR4
Maximum memory clock frequency 1600MHz
Configuration Hard PHY with hard memory controller
Clock rate of PHY and hard memory controller Half-rate, Quarter-rate
Data width (without ECC) 16-bit, 32-bit, 64-bit
Data width (with ECC) 24-bit, 40-bit, 72-bit
DQ width per group x8
Memory format Supports up to 32GB of memory.
  • Discrete components with up to 2 chip selects *
  • Non-3DS UDIMM or RDIMM with up to 2 chip selects *
  • SODIMM with up to 2 ranks *

* Only one differential memory clock output is provided; therefore, you must do one of the following:

  • Use single-rank discrete components, UDIMMs, or SODIMMs.
  • Use dual-rank components that require only one clock input (for example, dual-die packages).
  • Use RDIMMs that rely only on one clock input.
  • Use the single clock output to drive both clock inputs and confirm through simulation that the memory interface margins are not adversely affected by the double loading of the clock output.

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