18.104.22.168. Hard Memory Controller Features
|Memory standards support||
Supports DDR4 SDRAM.
|Memory devices support||Supports the following memory devices:
|3D Stacked Die support||Supports 2 and 4 height of 3D stacked die for DDR4 to increase memory capacity.|
|Memory controller bypass mode (Future support.)||You can use this configurable mode to bypass the hard memory controller and use your own customized controller.|
|Interface protocols support||
|Rate support||The legal options are:
|Configurable memory interface width||Supports data widths from 8 to 72 bits, in 8 bit increments|
|Multiple ranks support||Supports:
Able to accept burst lengths of 1–127 on the local interface of the controller and map the bursts to efficient memory commands. For applications that must strictly adhere to the Avalon® memory-mapped interface specification, the maximum burst length is 64.
No burst chop support for DDR4.
|Efficiency optimization features||
|Starvation counter||Ensures all requests are served after a predefined time out period, which ensures that low priority access are not left behind while reordering data for efficiency.|
|Bank interleaving||Able to issue read or write commands continuously to "random" addresses. You must correctly cycle the bank addresses.|
|On-die termination||The controller controls the on-die termination signal for the memory. This feature improves signal integrity and simplifies your board design.|
|Power saving features||
|User ZQ calibration||Long or short ZQ calibration request for DDR4.|
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