External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 3/28/2022
Public

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11.10.3.1.1. Global Parameter Table

The Global Parameter Table’s base address is 0x0500_0000 (which is the base address of the user RAM).
Table 173.  Global Parameters
Offset from GPT Base Field Name Field Width (in bytes) Description
0x0 gpt_GLOBAL_PAR_VER 4 Global Parameter Table version number.
0x4 gpt_NIOS_C_VER 4 Firmware version.
0x8 gpt_COLUMN_ID 4 ID of I/O row.
0xC gpt_NUM_IOPACKS 4 Maximum number of I/O tiles in the row that can be used as memory interface.
0x10 gpt_NIOS_CLK_FREQ_KHZ 4 Nios clock frequency (KHz).
0x14 gpt_PARAM_TABLE_SIZE 4 Size (in bytes) of the global and mem interface parameter tables combined.
0x1C gpt_GLOBAL_CAL_CONFIG 4 Asserts whether the debug toolkit is enabled (enabled if bits 0 and 2 are asserted).
0x20 gpt_SLAVE_CLK_DIVIDER 4 Divider for the calbus clock. Value 0 may be observed, indicating that firmware set an optimal value, assuming there is no other master accessing the calbus at the same time.
0x24 gpt_INTERFACE_PAR_PTRS 4 Pointers to memory interface parameter tables. The number of array elements is equal to gpt_NUM_IOPACKS.

offset 0x24 contains the pointer to the first interface (interface ID=0).

offset 0x28 contains the pointer to the second interface (interface ID=1).

offset 0x32 contains the pointer to the third interface, and so forth.

The index of the cal_bus to which an interface is connected determines its interface ID. An interface connected to cal_bus_0 is interface 0, while an interface connected to cal_bus_1 is interface 1, and so forth.

bit[31:16]: Reserved.

bit [15:0]: The pointer to memory interface parameter table, coded as the offset from the start of the user RAM. When a pointer has value 0, it means the memory interface is not used and its parameter table does not exist.

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