External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 3/28/2022
Public

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11.10.1. Enabling the On-Chip Debug Port

To export the cal_debug port, set the Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port parameter to Export, when parameterizing the emif_cal IP.
Figure 216. Enabling the On-Chip Debug Port
You may then create your own logic to perform the desired read/write commands on the cal_debug Avalon® memory-mapped interface.
Figure 217. Connecting Your Own Logic

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