External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 3/28/2022
Public

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4.1.2.4. pll_locked for QDR-IV

PLL locked signal
Table 43.  Interface: pll_lockedInterface type: Conduit
Port Name Direction Description
pll_locked Output PLL lock signal to indicate whether the PLL has locked

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