External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 3/28/2022
Public

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6.5.5.5. Power Delivery Recommendations for the Memory / DIMM Side

This topic describes power distribution network (PDN) design guidelines for one DIMM per channel (1DPC) and two DIMMs per channel (2DPC) memory interfaces at the DIMM/memory side.
Note: For information on power distribution network design at the FPGA to meet timing margins, refer to the AG014 PDN design guideline.

In the following table, the number of decoupling capacitors is based on a single channel. If multiple channels are sharing the same power rail at the DIMM, the number of decoupling capacitors at the DIMM must be scaled accordingly.

Physically small decoupling capacitors are recommended to minimize area, inductance, and resistance on the PDN path on the printed circuit board.

Table 113.  Required Decoupling Capacitors on the PCB for the Memory/DIMM Side
Memory Configuration Power Domain Decoupling Location Quantity × Value (size)
DDR4 1DPC VDDQ 4 near each side of DIMM connector close to VDDQ pins 8 × 47uF (0805)
4 near each side of DIMM connector close to VDDQ pins 8 × 1uF (0402)
VTT Place capacitor on VTT plane close to DIMM 1 × 47uF (0805)
Place capacitor on VTT plane close to DIMM 2 × 1uF (0402)
VPP Place capacitor close to DIMM 1 × 47uF (0805)
Place capacitor close to DIMM 1 × 1uF (0402)
VDDSPD Place capacitor close to DIMM 1 × 0.1uF (0402)
Place capacitor close to DIMM 1 × 2.2uF (0402)
DDR4 2DPC VDDQ 4 near each side of DIMM connector close to VDDQ pins 16 × 47uF (0805)
4 near each side of DIMM connector close to VDDQ pins 16 × 1uF (0402)
VTT Place capacitor on VTT plane close to DIMM 1 × 47uF (0805)
Place capacitor on VTT plane close to DIMM 4 × 1uF (0402)
VPP Place capacitor close to DIMM 2 × 47uF (0805)
Place capacitor close to DIMM 2 × 1uF (0402)
VDDSPD Place capacitor close to DIMM 1 × 0.1uF (0402)
Place capacitor close to DIMM 1 × 2.2uF (0402)