Video and Image Processing Suite User Guide

ID 683416
Date 4/04/2022
Public
Document Table of Contents

4. VIP Run-Time Control

All the Video and Image Processing IP cores have an optional simple run-time control interface that comprises a set of control and status registers, accessible through an Avalon Memory-Mapped (Avalon-MM) slave port.

All the IP cores have an optional simple run-time control interface that comprises a set of control and status registers, accessible through an Avalon-MM slave port. A run-time control configuration has a mandatory set of three registers for every IP core, followed by any function-specific registers.

Table 13.  Video and Image Processing IP Core Run-time Control Registers
Address Data Description
0 Bits 31:1 = X Bit 0 = Go Control register
1 Bits 31:1 = X Bit 1 = Status Status register
2 Core specific Interrupt register
Figure 19. Video and Image Processing Suite IP Cores BehaviorThe figure below illustrates the behavior of the Go and Status bits for every IP core when run-time control is configured, together with the steady-state running behavior that is always present.
Note: The Test Pattern Generator II and Mixer II IP cores deviate from this behavior. These IP cores start transmitting video before receiving any Avalon-ST Video packets.


When you enable run-time control, the Go bit gets deasserted by default. If you do not enable run-time control, the Go is asserted by default.

Every IP core retains address 2 in its address space to be used as an interrupt register. However this address is often unused because only some of the IP cores require interrupts.