Video and Image Processing Suite User Guide

ID 683416
Date 9/29/2022
Document Table of Contents

18.1. Guard Bands Parameter Settings

Table 57.  Guard Bands Parameter Settings
Parameter Value Description
Bits per color sample 4–16, Default = 8 Select the number of bits per color plane per pixel.
Number of color planes 1–3, Default = 2 Select the number of color planes per pixel.
Number of pixels in parallel 1, 2, 4, 8, Default = 1 Select the number of pixels transmitted per clock cycle.
Color planes transmitted in parallel On or Off Select whether to send the color planes in parallel or in sequence (serially).
4:2:2 data On or Off Turn on to indicate that the input data is 4:2:2 sampled.
Note: 4:2:2 mode does not support odd frame widths and heights.
Signed input data On or Off Turn on to indicate that the input data should be treated as signed 2’s complement numbers.
Signed output data On or Off Turn on to indicate that the output data should be treated as signed 2’s complement numbers
Run-time control On or Off Turn on to enable run-time control of the guard band values.
Note: When you turn on this parameter, the Go bit gets deasserted by default. When you turn off this parameter, the Go is asserted by default.
Lower/Upper guard band for color <0–3> 0 to (1Bits per color sample)-1 These parameters to define the guard bands for each color plane (up to 4 colors per pixel—color 0 is in the LSBs of the Avalon-ST Video data bus).

If you enable Run-time control, these values are just used as defaults at reset and may be overwritten at run time. These are unsigned values.

How user packets are handled
  • No user packets allowed
  • Discard all user packets received
  • Pass all user packets through to the output

If your design does not require the IP core to propagate user packets, then you may select to discard all user packets to reduce ALM usage.

If your design guarantees that the input data stream will never have any user packets, then you further reduce ALM usage by selecting No user packets allowed. In this case, the IP core may lock if it encounters a user packet.

Add extra pipelining registers On or Off Turn on this parameter to add extra pipeline stage registers to the data path. You must turn on this parameter to achieve:
  • Frequency of 150 MHz for Cyclone V devices
  • Frequencies above 250 MHz for Intel® Arria® 10, Intel® Cyclone® 10 GX, Arria V, or Stratix V devices
Reduced control register readback On or Off

If you do not turn on this parameter, the values of all the registers in the control slave interface can be read back after they are written.

If you turn on this parameter, you cannot read back the guard band values written through the control slave interface. The control, interrupt and status register values may still be read. This option reduces the size of the control slave logic.

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