Video and Image Processing Suite User Guide

ID 683416
Date 4/04/2022
Public
Document Table of Contents

17.2. Gamma Corrector Control Registers

The Gamma Corrector II IP core requires an Avalon-MM slave interface but the Gamma Corrector IP core can have up to three Avalon-MM slave interfaces.

The Gamma Corrector II IP core requires an Avalon-MM slave interface in all modes to enable run-time updating of the coefficient values. As is the convention with all VIP IP cores, when a control slave interface is included, the IP core resets into a stopped state and must be started by writing a ‘1’ to the Go bit of the control register before any input data is processed.

Table 57.  Gamma Corrector II Control Register Map
Address Register Description
0 Control Bit 0 of this register is the Go bit, all other bits are unused. Setting this bit to 0 causes the IP core to stop at the end of the next frame/field packet.
1 Status Bit 0 of this register is the Status bit, all other bits are unused. The IP core sets this address to 0 between frames. The IP core sets this address to 1 when it is processing data and cannot be stopped.
2 Interrupt This bit is not used because the IP core does not generate any interrupts.
3 Read bank
  • Set to 0 to select LUT bank 0
  • Set to 1 to select LUT bank 1
Ignored if dual bank mode is not enabled.
4 Write bank
  • Set to 0 to enable run-time updating of LUT bank 0
  • Set to 1 to enable run-time updating of LUT bank 1
Ignored if dual bank mode is not enabled.
5 Write color plane Selects to which color plane (LUT) the writes to the register map will be applied.
6 – 5+2 N where N is the number of bits per symbol LUT contents Each register aliases to one address in the selected write color of the selected write bank.
Note: The values written to registers 6 and above cannot be read back in any mode.