Video and Image Processing Suite User Guide

ID 683416
Date 4/04/2022
Document Table of Contents 4:2:0 Clocked Video

The CVI II and CVO II IP cores are agnostic of the video standard being driven through them.

Figure 18. CVI/CVO Map DataFigure below shows how a CVI II IP core, configured for 1 pixel in parallel with 3 color planes per pixel, maps all input pixels to the same, 3 color plane output pixel.

For 4:2:2, the “empty” data on the unused input data line becomes a color plane of “empty” data at the output of the CVI II. Likewise, the 4:2:0 triplet gets mapped into a single 3 color plane pixel at the output. This has a significant impact on handling 4:2:0.

The CVI II IP core automatically creates control packets where the horizontal width is half the real frame width. To select its timing parameters, the CVO II IP core compares the control packet dimensions against those held in the mode banks. To match a 4:2:0 control packet, the mode bank width must be recorded as half of the actual frame dimension so that it matches the control packet. If the full width is entered to the mode bank, the correct timing parameters will not be matched.