Video and Image Processing Suite User Guide

ID 683416
Date 4/04/2022
Public
Document Table of Contents

7.3.2. Interrupts

The Clocked Video Input IP produces a single interrupt line.
Table 19.  Internal InterruptsThe table lists the internal interrupts of the interrupt line.
IP Core Internal Interrupts Description
Clocked Video Input II IP Status update interrupt Triggers when the stable bit, the resolution valid bit, the overflow sticky bit, or the picture drop sticky bit of the Status register changes value.
End of field/frame interrupt
  • If the synchronization settings are set to Any field first, triggers on the falling edge of the v sync.
  • If the synchronization settings are set to F1 first, triggers on the falling edge of the F1 v sync.
  • If the synchronization settings are set to F0 first, triggers on the falling edge of the F0 v sync.

You can use this interrupt to trigger the reading of the ancillary packets from the control interface before the packets are overwritten by the next frame.

You can independently enable these interrupts using bits [2:1] of the Control register. You can read the interrupt values using bits [2:1] of the Interrupt register. Writing 1 to either of these bits clears the respective interrupt.