Video and Image Processing Suite User Guide

ID 683416
Date 4/04/2022
Public
Document Table of Contents

9. Mixer II IP Core

The Mixer II IP core mixes together multiple image layers.

The run-time control is partly provided by an Avalon-MM slave port with registers for the location, and on or off status of each foreground layer. The dimensions of each layer are then specified by Avalon-ST Video control packets.

  • Each foreground layer must be driven by a frame buffer or frame reader so that data can be provided at the correct time.
    • If the Synchronize background to layer 0 parameter is enabled, the input connected to layer 0 is used as the background layer and does not have to be driven by a frame buffer or frame reader.
    • If the Synchronize background to layer 0 parameter is disabled, all layers are treated as foreground layers and must be driven by a frame buffer or frame reader.
  • Each layer must fit within the dimensions of the background layer.

    To display the layers correctly:

    • The rightmost edge of each layer (width + X offset) must fit within the dimensions of the background layer.
    • The bottom edge of each layer (height + Y offset) must fit within the dimensions of the background layer.
Note: If these conditions are not met for any layers, the Mixer II IP core will not display those layers. However, the corresponding inputs will be consumed and will not get displayed.
The Mixer II IP core has the following features:
  • Supports picture-in-picture mixing and image blending with per-pixel and static value alpha support.
  • Supports dynamic changing of location and size of each layer during run time.
  • Supports dynamic changing of layers positioning during run time.
  • Allows the individual layers to be switched on and off.
  • Supports up to 8 pixels in parallel.
  • Supports up to 20 inputs.
  • Includes built in test pattern generator as background layer if required.
  • Supports low-latency mode by using layer 0 as background layer.

The Mixer II IP core reads the control data in two steps at the start of each frame. The buffering happens inside the IP core so that the control data can be updated during the frame processing without unexpected side effects.

The first step occurs after the IP core processes and transmits all the non-image data packets of the background layer, and it has received the header of an image data packet of type 0 for the background. At this stage, the on/off status of each layer is read. A layer can be:
  • disabled (0),
  • active and displayed (1), or
  • consumed but not displayed (2)
The maximum number of image layers mixed cannot be changed dynamically and must be set in the parameter editor.

The IP core processes the non-image data packets of each active foreground layer, displayed or consumed, in a sequential order, layer 1 first. The IP core integrally transmits the non-image data packets from the background layer. The IP core treats the non-image data packets from the foreground layers differently depending on their type.

  • Control packets (type 15)— processed to extract the width and height of each layer and are discarded on the fly.
  • Other/user packets (types 1–14)—propagated unchanged.

The second step corresponds to the usual behavior of other Video and Image Processing IP cores that have an Avalon-MM slave interface. After the IP core has processed and/or propagated the non-image data packets from the background layer and the foreground layers, it waits for the Go bit to be set to 1 before reading the top left position of each layer.

Consequently, the behavior of the Mixer II IP core differs slightly from the other Video and Image Processing IP cores, as illustrated by the following pseudo-code:
go = 0;
while (true)
{
	status = 0;
	read_non_image_data_packet_from background_layer();
	read_control_first_pass(); // Check layer status 
											(disable/displayed/consumed)
	for_each_layer layer_id
	{ 
		// process non-image data packets for displayed or consumed 
															layers
		if (layer_id is not disabled)
		{
		
		handle_non_image_packet_from_foreground_layer(layer_id); 
		}
	}
	while (go != 1)
		wait;
	status = 1;
	read_control_second_pass(); // Copies top-left coordinates to 
														internal registers
	send_image_data_header();
	process_frame();
}