Video and Image Processing Suite User Guide

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ID 683416
Date 4/04/2022
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Document Table of Contents
Document Table of Contents x
1. About the Video and Image Processing Suite 2. Avalon Streaming Video 3. Clocked Video 4. VIP Run-Time Control 5. Getting Started 6. VIP Connectivity Interfacing 7. Clocked Video Interface IPs 8. 2D FIR II IP Core 9. Mixer II IP Core 10. Clipper II IP Core 11. Color Plane Sequencer II IP Core 12. Color Space Converter II IP Core 13. Chroma Resampler II IP Core 14. Control Synchronizer IP Core 15. Deinterlacer II IP Core 16. Frame Buffer II IP Core 17. Gamma Corrector II IP Core 18. Configurable Guard Bands IP Core 19. Interlacer II IP Core 20. Scaler II IP Core 21. Switch II IP Core 22. Test Pattern Generator II IP Core 23. Trace System IP Core 24. Warp Lite Intel FPGA IP 25. Avalon-ST Video Stream Cleaner IP Core 26. Avalon-ST Video Monitor IP Core 27. VIP IP Core Software Control 28. Security Considerations 29. Video and Image Processing Suite User Guide Archives 30. Document Revision History for the Video and Image Processing Suite User Guide A. Avalon-ST Video Verification IP Suite
1. About the Video and Image Processing Suite x
1.1. Release Information 1.2. Device Family Support 1.3. Latency 1.4. In-System Performance and Resource Guidance 1.5. Stall Behavior and Error Recovery
2. Avalon Streaming Video x
2.1. Avalon-ST Video Configuration Types 2.2. Avalon-ST Video Packet Types 2.3. Avalon-ST Video Operation 2.4. Avalon-ST Video Error Cases
2.2. Avalon-ST Video Packet Types x
2.2.1. Avalon-ST Video Control Packets 2.2.2. Avalon-ST Video Video Packets 2.2.3. Avalon-ST Video User Packets
3. Clocked Video x
3.1. Video Formats
3.1. Video Formats x
3.1.1. Embedded Synchronization Format: Clocked Video Output 3.1.2. Embedded Synchronization Format: Clocked Video Input 3.1.3. Separate Synchronization Format 3.1.4. Video Locked Signal 3.1.5. Clocked Video and 4:2:0 Chroma Subsampling
3.1.1. Embedded Synchronization Format: Clocked Video Output x
3.1.1.1. Clocked Video Output and SDI II TX Interface
3.1.5. Clocked Video and 4:2:0 Chroma Subsampling x
3.1.5.1. Avalon-ST Video Control Packets for 4:2:0 Video 3.1.5.2. 4:2:0 Clocked Video 3.1.5.3. Resampling 4:2:0
5. Getting Started x
5.1. IP Catalog and VIP Parameter Editor 5.2. Installing and Licensing IP Cores
5.1. IP Catalog and VIP Parameter Editor x
5.1.1. Specifying IP Core Parameters and Options
5.2. Installing and Licensing IP Cores x
5.2.1. Intel® FPGA IP Evaluation Mode
6. VIP Connectivity Interfacing x
6.1. Avalon-ST Color Space Mappings
6.1. Avalon-ST Color Space Mappings x
6.1.1. Interfacing with High-Definition Multimedia Interface (HDMI) 6.1.2. Interfacing with DisplayPort 6.1.3. Interfacing with Serial Digital Interface (SDI) 6.1.4. Unsupported SDI Mappings 6.1.5. 12G-SDI
6.1.5. 12G-SDI x
6.1.5.1. 12G-SDI with Clocked Video Input II 6.1.5.2. 12G-SDI with Clocked Video Output II
7. Clocked Video Interface IPs x
7.1. Supported Features for Clocked Video Output II IP 7.2. Control Port 7.3. Clocked Video Input IP Format Detection 7.4. Clocked Video Output IP Video Modes 7.5. Clocked Video Output II Latency Mode 7.6. Generator Lock 7.7. Underflow and Overflow 7.8. Timing Constraints 7.9. Handling Ancillary Packets 7.10. Modules for Clocked Video Input II IP Core 7.11. Clocked Video Input II Signals, Parameters, and Registers 7.12. Clocked Video Output II Signals, Parameters, and Registers
7.3. Clocked Video Input IP Format Detection x
7.3.1. Format Detection in Clocked Video Input II 7.3.2. Interrupts
7.4. Clocked Video Output IP Video Modes x
7.4.1. Interrupts
7.11. Clocked Video Input II Signals, Parameters, and Registers x
7.11.1. Clocked Video Input II Interface Signals 7.11.2. Clocked Video Input II Parameter Settings 7.11.3. Clocked Video Input II Control Registers
7.12. Clocked Video Output II Signals, Parameters, and Registers x
7.12.1. Clocked Video Output II Interface Signals 7.12.2. Clocked Video Output II Parameter Settings 7.12.3. Clocked Video Output II Control Registers
8. 2D FIR II IP Core x
8.1. 2D FIR Filter Processing 8.2. 2D FIR Filter Precision 8.3. 2D FIR Coefficient Specification 8.4. 2D FIR Filter Symmetry 8.5. Result to Output Data Type Conversion 8.6. Edge-Adaptive Sharpen Mode 8.7. 2D FIR Filter Parameter Settings 8.8. 2D FIR Filter Control Registers
8.4. 2D FIR Filter Symmetry x
8.4.1. No Symmetry 8.4.2. Horizontal Symmetry 8.4.3. Vertical Symmetry 8.4.4. Horizontal and Vertical Symmetry 8.4.5. Diagonal Symmetry
8.6. Edge-Adaptive Sharpen Mode x
8.6.1. Edge Detection 8.6.2. Filtering 8.6.3. Precision
9. Mixer II IP Core x
9.1. Alpha Blending 9.2. Mixer II Parameter Settings 9.3. Mixer II Control Registers 9.4. Layer Mapping 9.5. Low-Latency Mode
10. Clipper II IP Core x
10.1. Clipper II Parameter Settings 10.2. Clipper II Control Registers
11. Color Plane Sequencer II IP Core x
11.1. Combining Color Patterns 11.2. Rearranging Color Patterns 11.3. Splitting and Duplicating 11.4. Handling of Subsampled Data 11.5. Handling of Non-Image Avalon-ST Packets 11.6. Color Plane Sequencer Parameter Settings
12. Color Space Converter II IP Core x
12.1. Input and Output Data Types 12.2. Color Space Conversion 12.3. Result of Output Data Type Conversion 12.4. Color Space Converter Parameter Settings 12.5. Color Space Conversion Control Registers
12.2. Color Space Conversion x
12.2.1. Predefined Conversions
13. Chroma Resampler II IP Core x
13.1. Chroma Resampler Algorithms 13.2. Chroma Resampler Parameter Settings 13.3. Chroma Resampler Control Registers
13.1. Chroma Resampler Algorithms x
13.1.1. Nearest Neighbor 13.1.2. Bilinear 13.1.3. Filtered
14. Control Synchronizer IP Core x
14.1. Using the Control Synchronizer IP Core 14.2. Control Synchronizer Parameter Settings 14.3. Control Synchronizer Control Registers
15. Deinterlacer II IP Core x
15.1. Deinterlacing Algorithm Options 15.2. Deinterlacing Algorithms 15.3. Run-time Control 15.4. Pass-Through Mode for Progressive Frames 15.5. Cadence Detection (Motion Adaptive Deinterlacing Only) 15.6. Avalon-MM Interface to Memory 15.7. Motion Adaptive Mode Bandwidth Requirements 15.8. Avalon-ST Video Support 15.9. 4K Video Passthrough Support 15.10. Behavior When Unexpected Fields are Received 15.11. Handling of Avalon-ST Video Control Packets 15.12. Deinterlacer II Parameter Settings 15.13. Deinterlacing Control Registers
15.2. Deinterlacing Algorithms x
15.2.1. Vertical Interpolation (Bob) 15.2.2. Field Weaving (Weave) 15.2.3. Motion Adaptive 15.2.4. Motion Adaptive High Quality (Sobel Edge Interpolation)
15.9. 4K Video Passthrough Support x
15.9.1. Approach A 15.9.2. Approach B
15.13. Deinterlacing Control Registers x
15.13.1. Scene Change Motion Multiplier Value 15.13.2. Tuning Motion Shift and Motion Scale Registers
16. Frame Buffer II IP Core x
16.1. Double Buffering 16.2. Triple Buffering 16.3. Locked Frame Rate Conversion 16.4. Handling of Avalon-ST Video Control Packets and User Packets 16.5. Frame Buffer Parameter Settings 16.6. Frame Buffer Application Examples 16.7. Frame Buffer Control Registers
16.3. Locked Frame Rate Conversion x
16.3.1. Converting Frame Rates
16.7. Frame Buffer Control Registers x
16.7.1. Frame Writer Only Mode 16.7.2. Frame Reader Only Mode 16.7.3. Memory Map for Frame Reader or Writer Configurations
17. Gamma Corrector II IP Core x
17.1. Gamma Corrector Parameter Settings 17.2. Gamma Corrector Control Registers
18. Configurable Guard Bands IP Core x
18.1. Guard Bands Parameter Settings 18.2. Configurable Guard Bands Control Registers
19. Interlacer II IP Core x
19.1. Interlacer Parameter Settings 19.2. Interlacer Control Registers
20. Scaler II IP Core x
20.1. Nearest Neighbor Algorithm 20.2. Bilinear Algorithm 20.3. Polyphase and Bicubic Algorithm 20.4. Edge-Adaptive Scaling Algorithm 20.5. Scaler II Parameter Settings 20.6. Scaler II Control Registers
20.2. Bilinear Algorithm x
20.2.1. Bilinear Algorithmic Description
20.3. Polyphase and Bicubic Algorithm x
20.3.1. Double-Buffering 20.3.2. Polyphase Algorithmic Description 20.3.3. Choosing and Loading Coefficients
21. Switch II IP Core x
21.1. Switch II Parameter Settings 21.2. Switch II Control Registers
22. Test Pattern Generator II IP Core x
22.1. Test Patterns 22.2. Output Subsampling and Color Space 22.3. Generation of Avalon-ST Video Control Packets and Run-Time Control 22.4. Test Pattern Generator II Parameter Settings 22.5. Test Pattern Generator II Control Registers
22.1. Test Patterns x
22.1.1. Color Bars 22.1.2. Grayscale Bars 22.1.3. Black and White Bars 22.1.4. SDI Pathological 22.1.5. Uniform Background
23. Trace System IP Core x
23.1. Trace System Parameter Settings 23.2. Trace System Signals 23.3. Operating the Trace System from System Console
23.3. Operating the Trace System from System Console x
23.3.1. Loading the Project and Connecting to the Hardware 23.3.2. Trace Within System Console 23.3.3. TCL Shell Commands
24. Warp Lite Intel FPGA IP x
24.1. Warp Lite IP Release Information 24.2. About Image Warping 24.3. About the Warp Lite Intel FPGA IP 24.4. Operating the Warp Lite IP 24.5. Warp Lite IP Parameters 24.6. Warp Lite IP Control Registers' Map 24.7. Warp Lite IP Line Store 24.8. Warp Lite IP API
24.3. About the Warp Lite Intel FPGA IP x
24.3.1. Warp Definition Equations 24.3.2. Resampling and Interpolation
24.3.1. Warp Definition Equations x
24.3.1.1. Transform Matrix and Keystone Region Corners 24.3.1.2. Horizontal Flip Equation
24.7. Warp Lite IP Line Store x
24.7.1. Line Store RAM Utilization 24.7.2. Buffer Ingress and Egress Overlap
25. Avalon-ST Video Stream Cleaner IP Core x
25.1. Avalon-ST Video Protocol 25.2. Repairing Non-Ideal and Error Cases 25.3. Avalon-ST Video Stream Cleaner Parameter Settings 25.4. Avalon-ST Video Stream Cleaner Control Registers
26. Avalon-ST Video Monitor IP Core x
26.1. Packet Visualization 26.2. Monitor Settings 26.3. Avalon-ST Video Monitor Parameter Settings 26.4. Avalon-ST Video Monitor Control Registers
27. VIP IP Core Software Control x
27.1. HAL Device Drivers for Nios II SBT
28. Security Considerations x
28.1. Using Avalon-ST Video Monitor Debug Tools 28.2. Configuring Memory Subsystems
A. Avalon-ST Video Verification IP Suite x
A.1. Avalon-ST Video Class Library A.2. Example Tests A.3. Complete Class Reference A.4. Data Format
A.2. Example Tests x
A.2.1. Generating the Testbench Netlist A.2.2. Running the Test in Intel® Quartus® Prime Standard Edition A.2.3. Running the Test in Intel® Quartus® Prime Pro Edition A.2.4. Viewing the Video File A.2.5. Verification Files A.2.6. Constrained Random Test
A.2.5. Verification Files x
A.2.5.1. bfm_drivers.sv A.2.5.2. nios_control_model.sv
A.3. Complete Class Reference x
A.3.1. c_av_st_video_control A.3.2. c_av_st_video_data A.3.3. c_av_st_video_file_io A.3.4. c_av_st_video_item A.3.5. c_av_st_video_source_sink_base A.3.6. c_av_st_video_sink_bfm_’SINK A.3.7. c_av_st_video_source_bfm_’SOURCE A.3.8. c_av_st_video_user_packet A.3.9. c_pixel A.3.10. av_mm_transaction A.3.11. av_mm_master_bfm_`MASTER_NAME A.3.12. av_mm_slave_bfm_`SLAVE_NAME A.3.13. av_mm_control_register A.3.14. av_mm_control_base
1. About the Video and Image Processing Suite
2. Avalon Streaming Video
3. Clocked Video
4. VIP Run-Time Control
5. Getting Started
6. VIP Connectivity Interfacing
7. Clocked Video Interface IPs
8. 2D FIR II IP Core
9. Mixer II IP Core
10. Clipper II IP Core
11. Color Plane Sequencer II IP Core
12. Color Space Converter II IP Core
13. Chroma Resampler II IP Core
14. Control Synchronizer IP Core
15. Deinterlacer II IP Core
16. Frame Buffer II IP Core
17. Gamma Corrector II IP Core
18. Configurable Guard Bands IP Core
19. Interlacer II IP Core
20. Scaler II IP Core
21. Switch II IP Core
22. Test Pattern Generator II IP Core
23. Trace System IP Core
24. Warp Lite Intel FPGA IP
25. Avalon-ST Video Stream Cleaner IP Core
26. Avalon-ST Video Monitor IP Core
27. VIP IP Core Software Control
28. Security Considerations
29. Video and Image Processing Suite User Guide Archives
30. Document Revision History for the Video and Image Processing Suite User Guide
A. Avalon-ST Video Verification IP Suite

7.12.3. Clocked Video Output II Control Registers

Note: If you configure the design without enabling the control interface, the interrupt line (status_update_int) will not be generated. This is because the logic required to clear the interrupt will not be generated and therefore could not provide useful information.
Table 29.  Clocked Video Output II RegistersThe rows in the table are repeated in ascending order for each video mode. All of the ModeN registers are write only.
Address Register Description
0 Control
  • Bit 0 of this register is the Go bit. Setting this bit to 1 causes the CVO IP core to start video data output.
  • Bit 2 of the Control register is the Clear Underflow Register bit. When bit 2 of the Status register is set, a 1 should be written to this register to clear the underflow.
  • Bits 4 and 3 of the Control register are the Genlock control bits.
    • Setting bit 3 to 1 enables the synchronization outputs: vid_sof, vid_sof_locked, and vcoclk_div.
    • Setting bit 4 to 1, while bit 3 is 1, enables frame locking. The IP core attempts to align its vid_sof signal to the sof signal from the CVI IP core.
  • Bits 9 and 8 of the Control register are the interrupt enables, matching the position of the interrupt registers at address 2.
    • Setting bit 8 to 1 enables the status update interrupt.
    • Setting bit 9 to 1 enables the locked interrupt.
1 Status
  • Bit 0 of this register is the Status bit. This bit is asserted when the CVO IP core is producing data.
  • Bit 1 of the Status register is unused.
  • Bit 2 is the underflow sticky bit. When bit 2 is asserted, the output FIFO has underflowed. The underflow sticky bit stays asserted until a 1 is written to bit 2 of the Control register
  • Bit 3 is the frame locked bit. When bit 3 is asserted, the CVO IP core has aligned its start of frame to the incoming sof signal.
2 Interrupt Bits 9 and 8 are the interrupt status bits:
  • When bit 1 is asserted, the status update interrupt has triggered.
  • When bit 2 is asserted, the locked interrupt has triggered.
  • The interrupts stay asserted until a 1 is written to these bits.
3 Video Mode Match Before any user specified modes are matched, this register reads back 0 indicating the default values are selected. Once a match has been made, the register reads back in a one-hot fashion, e.g.

0x0001=Mode0

0x00020=Mode5
4 Bank Select Writes to the ModeN registers will be reflected to the mode bank selected by this register.

Up to 13 banks are available depending on parameterization. Selection is by standard binary encoding.

5 ModeN Control Video ModeN 1 Control.
  • Bit 0 of this register is the Interlaced bit.
    • Set to 1 for interlaced.
    • Set to 0 for progressive.
  • Bit 1 of this register is the sequential output control bit (only if the Allow output of color planes in sequence compile-time parameter is enabled).
    • Setting bit 1 to 1, enables sequential output from the CVO IP core (NTSC).
    • Setting bit 1 to 0, enables parallel output from the CVO IP core (1080p).
6 ModeN Sample Count Video mode N sample count. Specifies the active picture width of the field.
7 ModeN F0 Line Count Video mode N field 0/progressive line count. Specifies the active picture height of the field.
8 ModeN F1 Line Count Video mode N field 1 line count (interlaced video only). Specifies the active picture height of the field.
9 ModeN Horizontal Front Porch Video mode N horizontal front porch. Specifies the length of the horizontal front porch in samples.
10 ModeN Horizontal Sync Length Video mode N horizontal synchronization length. Specifies the length of the horizontal synchronization length in samples.
11 ModeN Horizontal Blanking Video mode N horizontal blanking period. Specifies the length of the horizontal blanking period in samples.
12 ModeN Vertical Front Porch Video mode N vertical front porch. Specifies the length of the vertical front porch in lines.
13 ModeN Vertical Sync Length Video mode 1 vertical synchronization length. Specifies the length of the vertical synchronization length in lines.
14 Mode1 Vertical Blanking Video mode N vertical blanking period. Specifies the length of the vertical blanking period in lines.
15 ModeN F0 Vertical Front Porch Video mode N field 0 vertical front porch (interlaced video only). Specifies the length of the vertical front porch in lines.
16 ModeN F0 Vertical Sync Length Video mode N field 0 vertical synchronization length (interlaced video only). Specifies the length of the vertical synchronization length in lines.
17 ModeN F0 Vertical Blanking Video mode N field 0 vertical blanking period (interlaced video only). Specifies the length of the vertical blanking period in lines.
18 ModeN Active Picture Line Video mode N active picture line. Specifies the line number given to the first line of active picture.
19 ModeN F0 Vertical Rising Video mode N field 0 vertical blanking rising edge. Specifies the line number given to the start of field 0's vertical blanking.
20 ModeN Field Rising Video mode N field rising edge. Specifies the line number given to the end of Field 0 and the start of Field 1.
21 ModeN Field Falling Video mode N field falling edge. Specifies the line number given to the end of Field 0 and the start of Field 1.
22 ModeN Standard The value output on the vid_std signal.
23 ModeN SOF Sample Start of frame sample register. The sample and subsample upon which the SOF occurs (and the vid_sof signal triggers):
  • Bits 1–0 are the subsample value.
  • Bits 15–2 are the sample value.
24 ModeN SOF Line SOF line register. The line upon which the SOF occurs measured from the rising edge of the F0 vertical sync.

This is a 13-bit register.

25 ModeN Vcoclk Divider Number of cycles of vid_clk (vcoclk) before vcoclk_div signal triggers.

This is a 14-bit register.

26 ModeN Ancillary Line The line to start inserting ancillary data packets.
27 ModeN F0 Ancillary Line The line in field F0 to start inserting ancillary data packets.
28 ModeN H-Sync Polarity Specify positive or negative polarity for the horizontal sync.
  • Bit 0 is 0 for falling edge pulses (negative polarity).
  • Bit 0 is 1 for rising edge hsync pulses (positive polarity).
29 ModeN V-Sync Polarity Specify positive or negative polarity for the vertical sync.
  • Bit 0 is 0 for falling edge pulses (negative polarity).
  • Bit 0 is 1 for rising edge vsync pulses (positive polarity).
30 ModeN Valid Video mode valid. Set to indicate that this mode is valid and can be used for video output.
Note:

To ensure the vid_f signal rises at the Field 0 blanking period and falls at the Field 1, use the following equations:

  • F rising edge line ≥ Vertical blanking rising edge line
  • F rising edge line < Vertical blanking rising edge line + (Vertical sync + Vertical front porch + Vertical back porch)
  • F falling edge line < active picture line
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