Video and Image Processing Suite User Guide

ID 683416
Date 4/04/2022
Public
Document Table of Contents

7.12.3. Clocked Video Output II Control Registers

Note: If you configure the design without enabling the control interface, the interrupt line (status_update_int) will not be generated. This is because the logic required to clear the interrupt will not be generated and therefore could not provide useful information.
Table 29.  Clocked Video Output II RegistersThe rows in the table are repeated in ascending order for each video mode. All of the ModeN registers are write only.
Address Register Description
0 Control
  • Bit 0 of this register is the Go bit. Setting this bit to 1 causes the CVO IP core to start video data output.
  • Bit 2 of the Control register is the Clear Underflow Register bit. When bit 2 of the Status register is set, a 1 should be written to this register to clear the underflow.
  • Bits 4 and 3 of the Control register are the Genlock control bits.
    • Setting bit 3 to 1 enables the synchronization outputs: vid_sof, vid_sof_locked, and vcoclk_div.
    • Setting bit 4 to 1, while bit 3 is 1, enables frame locking. The IP core attempts to align its vid_sof signal to the sof signal from the CVI IP core.
  • Bits 9 and 8 of the Control register are the interrupt enables, matching the position of the interrupt registers at address 2.
    • Setting bit 8 to 1 enables the status update interrupt.
    • Setting bit 9 to 1 enables the locked interrupt.
1 Status
  • Bit 0 of this register is the Status bit. This bit is asserted when the CVO IP core is producing data.
  • Bit 1 of the Status register is unused.
  • Bit 2 is the underflow sticky bit. When bit 2 is asserted, the output FIFO has underflowed. The underflow sticky bit stays asserted until a 1 is written to bit 2 of the Control register
  • Bit 3 is the frame locked bit. When bit 3 is asserted, the CVO IP core has aligned its start of frame to the incoming sof signal.
2 Interrupt Bits 9 and 8 are the interrupt status bits:
  • When bit 1 is asserted, the status update interrupt has triggered.
  • When bit 2 is asserted, the locked interrupt has triggered.
  • The interrupts stay asserted until a 1 is written to these bits.
3 Video Mode Match Before any user specified modes are matched, this register reads back 0 indicating the default values are selected. Once a match has been made, the register reads back in a one-hot fashion, e.g.

0x0001=Mode0

0x00020=Mode5

4 Bank Select Writes to the ModeN registers will be reflected to the mode bank selected by this register.

Up to 13 banks are available depending on parameterization. Selection is by standard binary encoding.

5 ModeN Control Video ModeN 1 Control.
  • Bit 0 of this register is the Interlaced bit.
    • Set to 1 for interlaced.
    • Set to 0 for progressive.
  • Bit 1 of this register is the sequential output control bit (only if the Allow output of color planes in sequence compile-time parameter is enabled).
    • Setting bit 1 to 1, enables sequential output from the CVO IP core (NTSC).
    • Setting bit 1 to 0, enables parallel output from the CVO IP core (1080p).
6 ModeN Sample Count Video mode N sample count. Specifies the active picture width of the field.
7 ModeN F0 Line Count Video mode N field 0/progressive line count. Specifies the active picture height of the field.
8 ModeN F1 Line Count Video mode N field 1 line count (interlaced video only). Specifies the active picture height of the field.
9 ModeN Horizontal Front Porch Video mode N horizontal front porch. Specifies the length of the horizontal front porch in samples.
10 ModeN Horizontal Sync Length Video mode N horizontal synchronization length. Specifies the length of the horizontal synchronization length in samples.
11 ModeN Horizontal Blanking Video mode N horizontal blanking period. Specifies the length of the horizontal blanking period in samples.
12 ModeN Vertical Front Porch Video mode N vertical front porch. Specifies the length of the vertical front porch in lines.
13 ModeN Vertical Sync Length Video mode 1 vertical synchronization length. Specifies the length of the vertical synchronization length in lines.
14 Mode1 Vertical Blanking Video mode N vertical blanking period. Specifies the length of the vertical blanking period in lines.
15 ModeN F0 Vertical Front Porch Video mode N field 0 vertical front porch (interlaced video only). Specifies the length of the vertical front porch in lines.
16 ModeN F0 Vertical Sync Length Video mode N field 0 vertical synchronization length (interlaced video only). Specifies the length of the vertical synchronization length in lines.
17 ModeN F0 Vertical Blanking Video mode N field 0 vertical blanking period (interlaced video only). Specifies the length of the vertical blanking period in lines.
18 ModeN Active Picture Line Video mode N active picture line. Specifies the line number given to the first line of active picture.
19 ModeN F0 Vertical Rising Video mode N field 0 vertical blanking rising edge. Specifies the line number given to the start of field 0's vertical blanking.
20 ModeN Field Rising Video mode N field rising edge. Specifies the line number given to the end of Field 0 and the start of Field 1.
21 ModeN Field Falling Video mode N field falling edge. Specifies the line number given to the end of Field 0 and the start of Field 1.
22 ModeN Standard The value output on the vid_std signal.
23 ModeN SOF Sample Start of frame sample register. The sample and subsample upon which the SOF occurs (and the vid_sof signal triggers):
  • Bits 1–0 are the subsample value.
  • Bits 15–2 are the sample value.
24 ModeN SOF Line SOF line register. The line upon which the SOF occurs measured from the rising edge of the F0 vertical sync.

This is a 13-bit register.

25 ModeN Vcoclk Divider Number of cycles of vid_clk (vcoclk) before vcoclk_div signal triggers.

This is a 14-bit register.

26 ModeN Ancillary Line The line to start inserting ancillary data packets.
27 ModeN F0 Ancillary Line The line in field F0 to start inserting ancillary data packets.
28 ModeN H-Sync Polarity Specify positive or negative polarity for the horizontal sync.
  • Bit 0 is 0 for falling edge pulses (negative polarity).
  • Bit 0 is 1 for rising edge hsync pulses (positive polarity).
29 ModeN V-Sync Polarity Specify positive or negative polarity for the vertical sync.
  • Bit 0 is 0 for falling edge pulses (negative polarity).
  • Bit 0 is 1 for rising edge vsync pulses (positive polarity).
30 ModeN Valid Video mode valid. Set to indicate that this mode is valid and can be used for video output.
Note:

To ensure the vid_f signal rises at the Field 0 blanking period and falls at the Field 1, use the following equations:

  • F rising edge line ≥ Vertical blanking rising edge line
  • F rising edge line < Vertical blanking rising edge line + (Vertical sync + Vertical front porch + Vertical back porch)
  • F falling edge line < active picture line