Video and Image Processing Suite User Guide

ID 683416
Date 4/04/2022
Document Table of Contents

16. Frame Buffer II IP Core

The Frame Buffer II IP core buffers video frames into external RAM.
The Frame Buffer II IP core offers the following features:
  • Buffers progressive and interlaced video fields.
  • Supports double and triple buffering with a range of options for frame dropping and repeating
    • When frame dropping and frame repeating are not allowed—the IP core provides a double-buffering function that can help solve throughput issues in the data path.
    • When frame dropping and/or frame repeating are allowed—the IP core provides a triple-buffering function that can be used to perform simple frame rate conversion.
  • Supports up to 8 pixels per transmission.
  • Supports a configurable inter-buffer offset to allow the best interleaving of DDR banks for maximum efficiency
  • Supports compile-time or run-time controlled variable buffer delay up to 4,095 frames
  • Supports reader-only or writer-only modes
  • Configurable user packet behavior

The Frame Buffer II IP core has two basic blocks:

  • Writer—stores input pixels in memory
  • Reader—retrieves video frames from the memory and produces them as outputs
Figure 67. Frame Buffer Block Diagram