Video and Image Processing Suite User Guide

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Date 4/04/2022
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7.12.1. Clocked Video Output II Interface Signals

Table 26.  Clocked Video Output II Signals
Signal Direction Description
main_reset_reset Input The IP core asynchronously resets when you assert this signal. You must deassert this signal synchronously to the rising edge of the clock signal.
main_clock_clk Input The main system clock. The IP core operates on the rising edge of this signal.
din_data Input din port Avalon-ST data bus. This bus enables the transfer of pixel data into the IP core.
din_endofpacket Input din port Avalon-ST endofpacket signal. This signal is asserted when the downstream device is ending a frame.
din_ready Output din port Avalon-ST ready signal. This signal is asserted when the IP core function is able to receive data.
din_startofpacket Input din port Avalon-ST startofpacket signal. Assert this signal when the downstream device is starting a new frame.
din_valid Input din port Avalon-ST valid signal. Assert this signal when the downstream device produces data.
din_empty Input din port Avalon-ST empty signal. This signal has a non zero value only when you set the Number of pixels in parallel parameter to be greater than 1. This signal specifies the number of pixel positions which are empty at the end of the din_endofpacket signal.
underflow Output Clocked video underflow signal. A signal corresponding to the underflow sticky bit of the Status register synchronized to vid_clk. This signal is for information only and no action is required if it is asserted.
Note: Present only if you turn on Use control port.
status_update_int Output control slave port Avalon-MM interrupt signal. When asserted, the status registers of the IP core have been updated and the master must read them to determine what has occurred.
Note: Present only if you turn on Use control port.
vid_clk Input Clocked video clock. All the video output signals are synchronous to this clock.
vid_data Output Clocked video data bus. This bus transfers video data out of the IP core.
vid_datavalid Output Clocked video data valid signal. Assert this signal when a valid sample of video data is present on vid_data.
Note: This signal is equivalent to the CVI II IP core's vid_de signal.
vid_f Output Clocked video field signal. For interlaced input, this signal distinguishes between field 0 and field 1. For progressive video, this signal is unused.
Note: For separate synchronization mode only.
vid_h Output Clocked video horizontal blanking signal. This signal is asserted during the horizontal blanking period of the video stream.
Note: For separate synchronization mode only.
vid_h_sync Output Clocked video horizontal synchronization signal. This signal is asserted during the horizontal synchronization period of the video stream.
Note: For separate synchronization mode only.
vid_ln Output Clocked video line number signal. Used with the SDI IP core to indicate the current line number when the vid_trs signal is asserted.
Note: For embedded synchronization mode only.
vid_mode_change Output Clocked video mode change signal. This signal is asserted on the cycle before a mode change occurs.
vid_std Output Video standard bus. Can be connected to the tx_std signal of the SDI IP core (or any other interface) to read from the Standard register.
vid_trs Output Clocked video time reference signal (TRS) signal. Used with the SDI IP core to indicate a TRS, when asserted.
Note: For embedded synchronization mode only.
vid_v Output Clocked video vertical blanking signal. This signal is asserted during the vertical blanking period of the video stream.
Note: For separate synchronization mode only.
vid_v_sync Output Clocked video vertical synchronization signal. This signal is asserted during the vertical synchronization period of the video stream.
Note: For separate synchronization mode only.
vcoclk_div Output A divided down version of vid_clk (vcoclk). Setting the Vcoclk Divider register to be the number of samples in a line produces a horizontal reference on this signal. A PLL uses this horizontal reference to synchronize its output clock.
Note: Present only if you turn on Use control port.
vid_sof Output Start of frame signal. A rising edge (0 to 1) indicates the start of the video frame as configured by the SOF registers.
Note: Present only if you turn on Use control port.
vid_sof_locked Output Start of frame locked signal. When asserted, the vid_sof signal is valid and can be used.
Note: Present only if you turn on Use control port.
sof Input Start of frame signal. A rising edge (0 to 1) indicates the start of the video frame as configured by the SOF registers. Connecting this signal to a CVI IP core allows the output video to be synchronized to this signal.
Note: Present only if you turn on Accept synchronization inputs.
sof_locked Input Start of frame locked signal. When asserted, the sof signal is valid and can be used.
Note: Present only if you turn on Accept synchronization inputs.
sdi_cvo_rden Input This signal connects to the SDI II IP core's tx_dataout_valid output signal. This signal indicates to the CVO II IP core to advance the state of the clocked video data and attributes.
Note: This signal is only available when you select the Embedded in video option for the Sync signals parameter. It will not be present for external sync interfaces such as DisplayPort and HDMI.
Table 27.  Control Signals for CVO II IP Cores
Signal Direction Description
av_address Input control slave port Avalon-MM address bus. Specifies a word offset into the slave address space.
Note: Present only if you turn on Use control port.
av_read Input control slave port Avalon-MM read signal. When you assert this signal, the control port drives new data onto the read data bus.
Note: Present only if you turn on Use control port.
av_readdata Output control slave port Avalon-MM read data bus. These output lines are used for read transfers.
Note: Present only if you turn on Use control port.
av_waitrequest Output
control slave port Avalon-MM wait request bus. This signal indicates that the slave is stalling the master transaction.
Note: Present only if you turn on Use control port.
av_write Input control slave port Avalon-MM write signal. When you assert this signal, the control port accepts new data from the write data bus.
Note: Present only if you turn on Use control port.
av_writedata Input control slave port Avalon-MM write data bus. These input lines are used for write transfers.
Note: Present only if you turn on Use control port.
av_byteenable Input control slave port Avalon-MM byteenable bus. These lines indicate which bytes are selected for write and read transactions.