Video and Image Processing Suite User Guide

ID 683416
Date 4/04/2022
Document Table of Contents

12.5. Color Space Conversion Control Registers

The width of each register in the Color Space Conversion control register map is 32 bits. To convert from fractional values, simply move the binary point right by the number of fractional bits specified in the user interface.

The control data is read once at the start of each frame and is buffered inside the IP core, so the registers can be safely updated during the processing of a frame.

Table 39.  Color Space Converter II Control RegisterThe table below describes the control register map for Color Space Converter II IP core.
Address Register Description
0 Control Bit 0 of this register is the Go bit, all other bits are unused. Setting this bit to 0 causes the IP core to stop the next time control information is read.
1 Status Bit 0 of this register is the Status bit, all other bits are unused.
2 Interrupts Unused.
3 Coeff-commit Writing a 1 to this location commits the writing of coefficient data. You must make this write to swap the coefficients currently in use with the latest set written to the register map.
4 Coefficient A0 The coefficient and summand registers use integer, signed 2’s complement numbers. Refer to Color Space Conversion.
5 Coefficient B0
6 Coefficient C0
7 Coefficient A1
8 Coefficient B1
9 Coefficient C1
10 Coefficient A2
11 Coefficient B2
12 Coefficient C2
13 Summand S0
14 Summand S1
15 Summand S2