1. About the Video and Image Processing Suite
2. Avalon Streaming Video
3. Clocked Video
4. VIP Run-Time Control
5. Getting Started
6. VIP Connectivity Interfacing
7. Clocked Video Interface IPs
8. 2D FIR II IP Core
9. Mixer II IP Core
10. Clipper II IP Core
11. Color Plane Sequencer II IP Core
12. Color Space Converter II IP Core
13. Chroma Resampler II IP Core
14. Control Synchronizer IP Core
15. Deinterlacer II IP Core
16. Frame Buffer II IP Core
17. Gamma Corrector II IP Core
18. Configurable Guard Bands IP Core
19. Interlacer II IP Core
20. Scaler II IP Core
21. Switch II IP Core
22. Test Pattern Generator II IP Core
23. Trace System IP Core
24. Warp Lite Intel FPGA IP
25. Avalon-ST Video Stream Cleaner IP Core
26. Avalon-ST Video Monitor IP Core
27. VIP IP Core Software Control
28. Security Considerations
29. Video and Image Processing Suite User Guide Archives
30. Document Revision History for the Video and Image Processing Suite User Guide
A. Avalon-ST Video Verification IP Suite
7.1. Supported Features for Clocked Video Output II IP
7.2. Control Port
7.3. Clocked Video Input IP Format Detection
7.4. Clocked Video Output IP Video Modes
7.5. Clocked Video Output II Latency Mode
7.6. Generator Lock
7.7. Underflow and Overflow
7.8. Timing Constraints
7.9. Handling Ancillary Packets
7.10. Modules for Clocked Video Input II IP Core
7.11. Clocked Video Input II Signals, Parameters, and Registers
7.12. Clocked Video Output II Signals, Parameters, and Registers
15.1. Deinterlacing Algorithm Options
15.2. Deinterlacing Algorithms
15.3. Run-time Control
15.4. Pass-Through Mode for Progressive Frames
15.5. Cadence Detection (Motion Adaptive Deinterlacing Only)
15.6. Avalon-MM Interface to Memory
15.7. Motion Adaptive Mode Bandwidth Requirements
15.8. Avalon-ST Video Support
15.9. 4K Video Passthrough Support
15.10. Behavior When Unexpected Fields are Received
15.11. Handling of Avalon-ST Video Control Packets
15.12. Deinterlacer II Parameter Settings
15.13. Deinterlacing Control Registers
A.3.1. c_av_st_video_control
A.3.2. c_av_st_video_data
A.3.3. c_av_st_video_file_io
A.3.4. c_av_st_video_item
A.3.5. c_av_st_video_source_sink_base
A.3.6. c_av_st_video_sink_bfm_’SINK
A.3.7. c_av_st_video_source_bfm_’SOURCE
A.3.8. c_av_st_video_user_packet
A.3.9. c_pixel
A.3.10. av_mm_transaction
A.3.11. av_mm_master_bfm_`MASTER_NAME
A.3.12. av_mm_slave_bfm_`SLAVE_NAME
A.3.13. av_mm_control_register
A.3.14. av_mm_control_base
21. Switch II IP Core
The Switch II IP core enables the connection of input video streams to output video streams.
You can configure the connections at run time through a control input.
The Switch II IP core offers the following features:
- Connects up to twelve input videos to twelve output videos.
- Does not combine streams.
- Each input to the IP core drives multiple outputs.
- Each output is driven by one input.
- Any input can be disabled when not routed to an output.
- Programs each disabled input to be in either stall or consume mode.
- A stalled input pulls its ready signal low.
- A consumed input pulls its ready signal high.
- Supports up to 8 pixels per transmission.
The routing configuration of the Switch II IP core is run-time configurable through the use of an Avalon-MM slave control port. You can write to the registers of the control port at anytime but the IP core loads the new values only when it is stopped. Stopping the IP core causes all the input streams to be synchronized at the end of an Avalon-ST Video image packet.
You can load a new configuration in one of the following ways:
- Writing a 0 to the Go register, waiting for the Status register to read 0 and then writing a 1 to the Go register.
- Writing a 1 to the Output Switch register performs the same sequence but without the need for user intervention. This the recommended way to load a new configuration.
Note: The status bit in the Switch II IP core's Status register is different from the status bit of the other VIP IP cores. The standard status indication has little value for this IP core because it potentially has multiple video streams passing through the core. For this reason, if the status of the video processing is required for synchronization purposes, use the status bit value(s) from the block(s) either upstream or downstream of the Switch II IP core.