Video and Image Processing Suite User Guide

ID 683416
Date 4/04/2022
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7.11.1. Clocked Video Input II Interface Signals

Table 22.  Clocked Video Input II Signals
Signal Direction Description
main_reset_reset Input The IP core asynchronously resets when you assert this signal. You must deassert this signal synchronously to the rising edge of the clock signal.
main_clock_clk Input The main system clock. The IP core operates on the rising edge of this signal.
dout_data Output dout port Avalon-ST data bus. This bus enables the transfer of pixel data out of the IP core.
dout_endofpacket Output dout port Avalon-ST endofpacket signal. This signal is asserted when the IP core is ending a frame.
dout_ready Input dout port Avalon-ST ready signal. The downstream device asserts this signal when it is able to receive data.
dout_startofpacket Output dout port Avalon-ST startofpacket signal. This signal is asserted when the IP core is starting a new frame.
dout_valid Output dout port Avalon-ST valid signal. This signal is asserted when the IP core produces data.
dout_empty Output dout port Avalon-ST empty signal. This signal has a non-zero value only when you set the Number of pixels in parallel parameter to be greater than 1. This signal specifies the number of pixel positions which are empty at the end of the dout_endofpacket signal.
status_update_int Output control slave port Avalon-MM interrupt signal. When asserted, the status registers of the IP core have been updated and the master must read them to determine what has occurred.
Note: Present only if you turn on Use control port.
vid_clk Input Clocked video clock. All the video input signals are synchronous to this clock.
vid_data Input Clocked video data bus. This bus enables the transfer of video data into the IP core.
vid_de Input Clocked video data enable signal. The driving core asserts this signal to indicate that the data on vid_data is part of the active picture region of an incoming video. This signal must be driven for correct operation of the IP core.
Note: For separate synchronization mode only.
vid_datavalid Input Enabling signal for the CVI II IP core. The IP core only reads the vid_data, vid_de, vid_h_sync, vid_v_sync, vid_std, and vid_f signals when vid_datavalid is 1. This signal allows the CVI II IP core to support oversampling during when the video runs at a higher rate than the pixel clock.
Note: If you are not oversampling your input video, tie this signal high.
vid_locked Input Clocked video locked signal. Assert this signal when a stable video stream is present on the input. Deassert this signal when the video stream is removed.

When 0, this signal triggers an early end of output frame packet and does not reset the internal registers. When this signal recovers after 0, if the system is not reset from outside, the first frame may have leftover pixels from the lock-lost frame,

vid_f Input Clocked video field signal. For interlaced input, this signal distinguishes between field 0 and field 1. For progressive video, you must deassert this signal.
Note: For separate synchronization mode only.
vid_v_sync Input Clocked video vertical synchronization signal. Assert this signal during the vertical synchronization period of the video stream.
Note: For separate synchronization mode only.
vid_h_sync Input Clocked video horizontal synchronization signal. Assert this signal during the horizontal synchronization period of the video stream.
Note: For separate synchronization mode only.
vid_hd_sdn Input Clocked video color plane format selection signal . This signal distinguishes between sequential (when low) and parallel (when high) color plane formats.
Note: For run-time switching of color plane transmission formats mode only.
vid_std Input Video standard bus. Can be connected to the rx_std signal of the SDI IP core (or any other interface) to read from the Standard register.
vid_color_encoding Input This signal is captured in the Color Pattern register and does not affect the functioning of the IP core. It provides a mechanism for control processors to read incoming color space information if the IP core (e.g. HDMI RX core) driving the CVI II does not provide such an interface.

Tie this signal to low if no equivalent signal is available from the IP core driving CVI II.

vid_bit_width Input This signal is captured in the Color Pattern register and does not affect the functioning of the IP core. It provides a mechanism for control processors to read incoming video bit width information if the IP core (e.g. HDMI RX core) driving the CVI II does not provide such an interface.

Tie this signal to low if no equivalent signal is available from the IP core driving CVI II.

vid_total_sample_count Input The IP core creates this signal if you do not turn on the Extract the total resolution parameter. The CVI II IP core operates using this signal as the total horizontal resolution instead of an internally detected version.
Vid_total_line_count Input The IP core creates this signal if you do not turn on the Extract the total resolution parameter. The CVI II IP core operates using this signal as the total vertical resolution instead of an internally detected version.
sof Output Start of frame signal. A change of 0 to 1 indicates the start of the video frame as configured by the SOF registers. Connecting this signal to a CVO IP core allows the function to synchronize its output video to this signal.
sof_locked Output Start of frame locked signal. When asserted, the sof signal is valid and can be used.
refclk_div Output A single cycle pulse in-line with the rising edge of the h sync.
clipping Output Clocked video clipping signal. A signal corresponding to the clipping bit of the Status register synchronized to vid_clk.

This signal is for information only and no action is required if it is asserted.

padding Output Clocked video padding signal. A signal corresponding to the padding bit of the Status register synchronized to vid_clk.

This signal is for information only and no action is required if it is asserted.

overflow Output Clocked video overflow signal. A signal corresponding to the overflow sticky bit of the Status register synchronized to vid_clk. This signal is for information only and no action is required if it is asserted.
Note: Present only if you turn on Use control port.
vid_hdmi_duplication[3:0] Input If you select Remove duplicate pixels in the parameter, this 4-bit bus is added to the CVI II interface. You can drive this bus based on the number of times each pixel is duplicated in the stream (HDMI-standard compliant).
Table 23.  Control Signals for CVI II IP Cores
Signal Direction Description
av_address Input control slave port Avalon-MM address bus. Specifies a word offset into the slave address space.
Note: Present only if you turn on Use control port.
av_read Input control slave port Avalon-MM read signal. When you assert this signal, the control port drives new data onto the read data bus.
Note: Present only if you turn on Use control port.
av_readdata Output control slave port Avalon-MM read data bus. These output lines are used for read transfers.
Note: Present only if you turn on Use control port.
av_waitrequest Output
control slave port Avalon-MM wait request bus. This signal indicates that the slave is stalling the master transaction.
Note: Present only if you turn on Use control port.
av_write Input control slave port Avalon-MM write signal. When you assert this signal, the control port accepts new data from the write data bus.
Note: Present only if you turn on Use control port.
av_writedata Input control slave port Avalon-MM write data bus. These input lines are used for write transfers.
Note: Present only if you turn on Use control port.
av_byteenable Input control slave port Avalon-MM byteenable bus. These lines indicate which bytes are selected for write and read transactions.