Video and Image Processing Suite User Guide

ID 683416
Date 4/04/2022
Public
Document Table of Contents

22.5. Test Pattern Generator II Control Registers

The width of each register in the Test Pattern Generator II control register map is 16 bits. The control data is read once at the start of each frame and is buffered inside the IP cores, so that the registers can be safely updated during the processing of a frame or pair of interlaced fields.

After reading the control data, the Test Pattern Generator II IP core generates a control packet that describes the following image data packet. When the output is interlaced, the control data is processed only before the first field of a frame, although a control packet is sent before each field.

Table 72.  Test Pattern Generator II Control Register MapThis table describes the control register map for Test Pattern Generator II IP core.
Address Register Description
0 Control Bit 0 of this register is the Go bit..

Setting this bit to 0 causes the IP core to stop before control information is read.

When you enable run-time control, the Go bit gets deasserted by default. If you do not enable run-time control, the Go is asserted by default.

Bit 1 of this register enables or disables the black border in the bars test patterns. This bit gets deasserted (border disabled) at reset.

All other bits are unused.

1 Status Bit 0 of this register is the Status bit, all other bits are unused.

The IP core sets this address to 0 between frames. The IP core sets this address to 1 while it is producing data and cannot be stopped.

2 Interrupt Unused.
3 Reserved Reserved.
4 Output Width The width of the output frames or fields in pixels.
Note: Value from 32 up to the maximum specified in the parameter editor.
5 Output Height The progressive height of the output frames or fields in pixels.
Note: Value from 32 up to the maximum specified in the parameter editor.
6 Output interlacing The output interlacing standard.

Set to 0 for progressive, 1 for interlacing with F0 first, and 2 for interlacing with f1 first.

7 Pattern select The test pattern configuration to enable.

Write 0 for configuration 0, 1 for configuration 1, and so on.

8 R/Y value The value of the R (or Y) color sample when the test pattern is a uniform color background.
Note: Available only when the IP core is configured to produce a uniform color background and run-time control interface is enabled.
9 G/Cb value The value of the G (or Cb) color sample when the test pattern is a uniform color background.
Note: Available only when the IP core is configured to produce a uniform color background and run-time control interface is enabled.
10 B/Cr value The value of the B (or Cr) color sample when the test pattern is a uniform color background.
Note: Available only when the IP core is configured to produce a uniform color background and run-time control interface is enabled.