Video and Image Processing Suite User Guide

ID 683416
Date 4/04/2022
Public
Document Table of Contents

7.11.2. Clocked Video Input II Parameter Settings

Table 24.  Clocked Video Input II Parameter Settings
Parameter Value Description
Bits per pixel per color plane 4–20, Default = 8 Select the number of bits per pixel (per color plane).
Number of color planes 1–4, Default = 3 Select the number of color planes.
Color plane transmission format
  • Sequence
  • Parallel
Specify whether to transmit the color planes in sequence or in parallel. If you select multiple pixels in parallel, then select Parallel.
Number of pixels in parallel 1, 2, 4, or 8 Specify the number of pixels transmitted or received in parallel.
Field order
  • Field 0 first
  • Field 1 first
  • Any field first
Specify the field to synchronize first when starting or stopping the output.
Enable matching data packet to control by clipping On or Off

When there is a change in resolution,the control packet and video data packet transmitted by the IP core mismatch. Turn on this parameter if you want to clip the input video frame to match the resolution sent in control packet.

When the current input frame resolution is wider and/or taller than the one specified in the control packet, then the IP core clips them to match the control packet dimensions.

Enable matching data packet to control by padding On or Off

Turn on this parameter if you also want to pad the incoming frame if it is smaller and/or shorter than the resolution specified in the control packet.

Note: This parameter is available only when you turn on Enable matching data packet to control by clipping. Depending on the size of the mismatch, padding operation could lead to frame drops at the input.
Overflow handling On or Off

Turn this parameter if you want the to finish the current frame (with dummy pixel data) based on the resolution specified in the control packet if overflow happens.

The IP core waits for the FIFO to become empty before it starts the padding process.

By default (turned off), if an overflow is encountered, current frame is terminated abruptly.

Note: Depending on size of the frame left to finish and the back pressure from downstream IP, overflow handling operation could lead to frame drops at the input.
Sync signals
  • Embedded in video
  • On separate wires
Specify whether to embed the synchronization signal in the video stream or provide on a separate wire.
Support 6G and 12G-SDI On or Off Turn on to enable 6G-SDI or 12G-SDI support for CVI II IP core. Turning on this option will fix the number of pixels in parallel to 4.
Note: This option is available only when you select the Embedded in video option for the Sync signals parameter.
Allow color planes in sequence input On or Off Turn on if you want to allow run-time switching between sequential and parallel color plane transmission formats. The format is controlled by the vid_hd_sdn signal.
Extract field signal On or Off Turn on to internally generate the field signal from the position of the V sync rising edge.
Use vid_std bus On or Off Turn on if you want to use the video standard, vid_std.
Note: Platform Designer always generates the vid_std signal even when you turn off this parameter. The IP core samples and stores this signal in the Standard register to be read back for software control. If not needed, leave this signal disconnected.
Width of vid_std bus

External sync: 1–16, Default = 1

Embedded sync: 3, Default = 3

Specify the width of the vid_std bus, in bits.
Extract ancillary packets On or Off Turn on to extract the ancillary packets in embedded sync mode.
Depth of the ancillary memory 0–4096, Default = 0 Specify the depth of the ancillary packet RAM, in words.
Extract the total resolution On or Off Turn on to extract total resolution from the video stream.
Enable HDMI duplicate pixel removal
  • No duplicate pixel removal
  • Remove duplicate pixel
Specify whether to enable a block to remove duplicate pixels for low rate resolutions. When you select Remove duplicate pixel, the IP core generates an additional 4-bit port to connect to the HDMI IP core. This port extracts the duplication factor from the HDMI IP core.
Note: The CVI II IP core currently supports only duplication factors of 0 (no duplication) or 1 (each pixel transmitted twice).
Interlaced or progressive
  • Progressive
  • Interlaced
Specify the format to be used when no format is automatically detected.
Width 32–8192, Default = 1920 Specify the image width to be used when no format is automatically detected.
Height – frame/field 0 32–8192, Default = 1080 Specify the image height to be used when no format is automatically detected.
Height – field 1 32–8192, Default = 480 Specify the image height for interlaced field 1 to be used when no format is automatically detected.
Pixel FIFO size 32–4096, Default = 2048 Specify the required FIFO depth in pixels.
Video in and out use the same clock On or Off Turn on if you want to use the same signal for the input and output video image stream clocks.
Use control port On or Off Turn on to use the optional stop/go control port.