Video and Image Processing Suite User Guide

ID 683416
Date 4/04/2022
Public
Document Table of Contents

7.6. Generator Lock

Generator lock (Genlock) locks the timing of video outputs to a reference source. Sources that are locked to the same reference can be cleanly switched between on a frame boundary.

For Clocked Video Input II IP, the refclk_div signal is a pulse on the rising edge of the H sync which a PLL can align its output clock to.

Clocked Video Input II IP

For the Clocked Video Input II IP, the SOF signal produces a pulse on the rising edge of the V sync. For interlaced video, the pulse is only produced on the rising edge of the F0 field, not the F1 field. The IP indicates a start of frame by a rising edge on the SOF signal (0 to 1).