Visible to Intel only — GUID: bhc1411020031627
Ixiasoft
Visible to Intel only — GUID: bhc1411020031627
Ixiasoft
7.6. Generator Lock
For Clocked Video Input II IP, the refclk_div signal is a pulse on the rising edge of the H sync which a PLL can align its output clock to.
Clocked Video Input II IP
For the Clocked Video Input II IP, the SOF signal produces a pulse on the rising edge of the V sync. For interlaced video, the pulse is only produced on the rising edge of the F0 field, not the F1 field. The IP indicates a start of frame by a rising edge on the SOF signal (0 to 1).
Did you find the information on this page useful?
Feedback Message
Characters remaining: