Video and Image Processing Suite User Guide

ID 683416
Date 4/04/2022
Document Table of Contents

19. Interlacer II IP Core

The Interlacer II IP core converts streams of progressive frames into streams of alternating F0 and F1 fields by discarding either the odd lines (F0) or the even lines (F1). The output field rate is consequently equal to the input frame rate.

You can parameterize the Interlacer II IP core to implement a number of optional features:

  • Pass through or discard of interlaced fields received at the input.
  • Start interlaced output streams created from progressive input with either an F0 or F1 field.
  • Override the default alternating F0/F1 output sequence for progressive input frames preceded by control packets with interlaced nibbles indicating that the progressive frame was created by deinterlacing original interlaced content. When you enable this option, the following interlaced nibbles are detected:
    • 0000 and 0100 – progressive frames deinterlaced using F0 as the last field. These are interlaced back into F0 fields.
    • 0001 and 0101 – progressive frames deinterlaced using F1 as the last field. These are interlaced back into F1 fields.

You can also enable an Avalon-MM slave interface to control the behavior of the Interlacer II IP Core at run time. When you enable the Avalon-MM slave interface, you can enable or disable the optional features above at run time. Otherwise, their behavior is fixed by your selection in the parameter editor.

Enabling the Avalon-MM slave interface also allows you to enable and disable all interlacing of progressive frames at run time, giving the option of progressive passthrough. When interlacing progressive input, the interlacer automatically resets to a new F0/F1 sequence when a change of resolution is detected in the incoming control packets, starting again with an F0 or F1 fields as defined by your parameterization or run-time control settings. You may also reset the F0/F1 sequence at any point using the Avalon-MM slave interface (see Interlacer Control Registers for details).