Video and Image Processing Suite User Guide

ID 683416
Date 4/04/2022
Public
Document Table of Contents

7.12.2. Clocked Video Output II Parameter Settings

Table 28.  Clocked Video Output II Parameter Settings
Parameter Value Description
Image width/Active pixels 32–8192, Default = 1920 Specify the image width by choosing the number of active pixels.
Image height/Active lines 32–8192, Default = 1200 Specify the image height by choosing the number of active lines.
Bits per pixel per color plane 4–20, Default = 8 Select the number of bits per pixel (per color plane).
Number of color planes 1–4, Default = 3 Select the number of color planes.
Color plane transmission format
  • Sequence
  • Parallel
Specify whether to transmit the color planes in sequence or in parallel. If you select multiple pixels in parallel, then select Parallel.
Allow output of channels in sequence On or Off
  • Turn on if you want to allow run-time switching between sequential formats, such as NTSC, and parallel color plane transmission formats, such as 1080p. The format is controlled by the ModeXControl registers.
  • Turn off if you are using multiple pixels in parallel.
Number of pixels in parallel 1, 2, 4, or 8 Specify the number of pixels transmitted or received in parallel.
Note: Number of pixels in parallel are only supported if you select On separate wires for the Sync signals parameter.
Interlaced video On or Off Turn off to use progressive video.
Sync signals
  • Embedded in video
  • On separate wires
Specify whether to embed the synchronization signal in the video stream or to provide the synchronization signal on a separate wire.
  • Embedded in video: You can set the active picture line, horizontal blanking, and vertical blanking values.
  • On separate wires: You can set horizontal and vertical values for sync, front porch, and back porch.
Support 6G and 12G-SDI On or Off Turn on to enable 6G-SDI or 12G-SDI support for CVO II IP core. Turning on this option will fix the number of pixels in parallel to 4.
Note: This option is available only when you select the Embedded in video option for the Sync signals parameter.
Default SDI video standard
  • SD
  • HD
  • 3GA (3G-SDI Level A)
  • 6GB (6G-SDI with 8 streams interleaved)
  • 12GA (12G-SDI with 8 streams interleaved)
Specify the default SDI video standard.
Note: This option is available only when you select the Embedded in video option for the Sync signals parameter.

6GB and 12GA options are available only when you turn on the Support 6G and 12G-SDI parameter.

Active picture line 32–65536, Default = 0 Specify the start of active picture line for Frame.
Frame/Field 1: Ancillary packet insertion line 32–65536, Default = 0 Specify the line where ancillary packet insertion starts.
Embedded syncs only - Frame/Field 1: Horizontal blanking 32–65536, Default = 0 Specify the size of the horizontal blanking period in pixels for Frame/Field 1.
Embedded syncs only - Frame/Field 1: Vertical blanking 32–65536, Default = 0 Specify the size of the vertical blanking period in pixels for Frame/Field 1.
Separate syncs only - Frame/Field 1: Horizontal sync 32–65536, Default = 44 Specify the size of the horizontal synchronization period in pixels for Frame/Field 1.
Separate syncs only - Frame/Field 1: Horizontal front porch 32–65536, Default = 88 Specify the size of the horizontal front porch period in pixels for Frame/Field 1.
Separate syncs only - Frame/Field 1: Horizontal back porch 32–65536, Default = 148 Specify the size of the horizontal back porch in pixels for Frame/Field 1.
Separate syncs only - Frame/Field 1: Vertical sync 32–65536, Default = 5 Specify the number of lines in the vertical synchronization period for Frame/Field 1.
Separate syncs only - Frame/Field 1: Vertical front porch 32–65536, Default = 4 Specify the number of lines in the vertical front porch period in pixels for Frame/Field 1.
Separate syncs only - Frame/Field 1: Vertical back porch 32–65536, Default = 36 Specify the number of lines in the vertical back porch in pixels for Frame/Field 1.
Interlaced and Field 0: F rising edge line 32–65536, Default = 0 Specify the line when the rising edge of the field bit occurs for Interlaced and Field 0.
Interlaced and Field 0: F falling edge line 32–65536, Default = 0 Specify the line when the falling edge of the field bit occurs for Interlaced and Field 0.
Interlaced and Field 0: Vertical blanking rising edge line 32–65536, Default = 0 Specify the line when the rising edge of the vertical blanking bit for Field 0 occurs for Interlaced and Field 0.
Interlaced and Field 0: Ancillary packet insertion line 32–65536, Default = 0 Specify the line where ancillary packet insertion starts.
Embedded syncs only - Field 0: Vertical blanking 32–65536, Default = 0 Specify the size of the vertical blanking period in pixels for Interlaced and Field 0.
Separate syncs only - Field 0: Vertical sync 32–65536, Default = 0 Specify the number of lines in the vertical synchronization period for Interlaced and Field 0.
Separate syncs only - Field 0: Vertical front porch 32–65536, Default = 0 Specify the number of lines in the vertical front porch period for Interlaced and Field 0.
Separate syncs only - Field 0: Vertical back porch 32–65536, Default = 0 Specify the number of lines in the vertical back porch period for Interlaced and Field 0.
Pixel FIFO size 32–(memory limit), Default = 1920 Specify the required FIFO depth in pixels, (limited by the available on-chip memory).
FIFO level at which to start output 0–(memory limit), Default = 1919 Specify the fill level that the FIFO must have reached before the output video starts.
Video in and out use the same clock On or Off Turn on if you want to use the same signal for the input and output video image stream clocks.
Use control port On or Off Turn on to use the optional Avalon-MM control port.
Generate synchronization outputs On or Off When you turn on Use control port, this option becomes available. Turning on this option generates the vid_vcoclk_div, vid_sof, and vid_sof_locked output signals. You can use these signals to generate timing reference signals to synchronize video.
Accept synchronization inputs On or Off When you turn on Generate synchronization outputs, this option becomes available. Turning on this option generates the sof and sof_locked input signals. These signals enable the CVO II IP core to align the synchronization outputs to within 1 line of inputs.
Set vco_clk_divider increment to pixels in parallel On or Off When you turn on Generate synchronization outputs, this option becomes available. Turning on this option enables you to set vco_clk_divider to increment in 2 different modes:
  • Increment in single counts until the divider value is reached.
  • Increment in steps equal to the value specified in the Number of pixels in parallel parameter.
The second increment allows vco_clk_div to keep step with the internal counters for the video output but introduces variation in the number of cycles between divclk pulses depending on the divclk value and how the value in the Number of pixels in parallel divides.
Low latency mode 0–1, Default = 0
  • Select 0 for regular completion mode. Each output frame initiated completes its timing before a new frame starts.
  • Select 1 for low latency mode. The IP core starts timing for a new frame immediately.
Run-time configurable video modes 1–13, Default = 1 Specify the number of run-time configurable video output modes that are required when you are using the Avalon-MM control port.
Note: This parameter is available only when you turn on Use control port.
Width of vid_std bus

External sync: 1–16, Default = 1

Embedded sync: 3, Default = 3

Select the width of the vid_std bus, in bits.