Video and Image Processing Suite User Guide

ID 683416
Date 4/04/2022
Public
Document Table of Contents
Give Feedback

9.3. Mixer II Control Registers

For efficiency reasons, the Video and Image Processing Suite IP cores buffer a few samples from the input stream even if they are not immediately processed. This implies that the Avalon-ST inputs for foreground layers assert ready high, and buffer a few samples even if the corresponding layer has been deactivated.

Table 34.  Mixer II Control Register MapThe table describes the control register map for Mixer II IP core.
Address Register Description
0 Control Bit 0 of this register is the Go bit, all other bits are unused. Setting this bit to 0 causes the IP core to stop the next time control information is read.
1 Status Bit 0 of this register is the Status bit, all other bits are unused.
2 Reserved Reserved for future use.
3 Background Width Change the width of the background layer for the next and all future frames.

Not available when the Synchronize background to layer 0 parameter is enabled.

4 Background Height Changes the height of the background layer for the next and all future frames.

Not available when the Synchronize background to layer 0 parameter is enabled.

5 Uniform background Red/Y Specifies the value for R (RGB) or Y (YCbCr). If you choose to use uniform background pattern, specify the individual R'G'B' or Y'Cb'Cr' values based on the color space you selected.

The uniform values match the width of bits per pixel up to a maximum of 16 bits. The IP core zero-pads values beyond 16 bits at the LSBs.

6 Uniform background Green/Cb Specifies the value for G (RGB) or Cb (YCbCr). If you choose to use uniform background pattern, specify the individual R'G'B' or Y'Cb'Cr' values based on the color space you selected.

The uniform values match the width of bits per pixel up to a maximum of 16 bits. The IP core zero-pads values beyond 16 bits at the LSBs.

7 Uniform background Blue/Cr Specifies the value for B (RGB) or Cr (YCbCr). If you choose to use uniform background pattern, specify the individual R'G'B' or Y'Cb'Cr' values based on the color space you selected.

The uniform values match the width of bits per pixel up to a maximum of 16 bits. The IP core zero-pads values beyond 16 bits at the LSBs.

8+5n Input X offset n X offset in pixels from the left edge of the background layer to the left edge of input n.
Note: n represents the input number, for example input 0, input 1, and so on.
9+5n Input Y offset n Y offset in pixels from the top edge of the background layer to the top edge of input n.
Note: n represents the input number, for example input 0, input 1, and so on.
10+5n Input control n
  • Set to bit 0 to enable input n.
  • Set to bit 1 to enable consume mode.
  • Set to bits 3:2 to enable alpha mode.
    • 00 – No blending, opaque overlay
    • 01 – Use static alpha value (available only when you turn on the Alpha Blending Enable parameter.)
    • 10 – Use alpha value from input stream (available only when you turn on the InputN alpha channel parameter.)
    • 11 – Unused
Note: n represents the input number, for example input 0, input 1, and so on.
11+5n Layer position n Specifies the layer mapping functionality for input n. Available only when you turn on the Layer Position Enable parameter.
Note: n represents the input number, for example input 0, input 1, and so on.
12+5n Static alpha n Specifies the static alpha value for input n with bit width matching the bits per pixel per color plane parameter. Available only when you turn on the Alpha Blending Enable parameter.
Note: n represents the input number, for example input 0, input 1, and so on.