Video and Image Processing Suite User Guide

ID 683416
Date 4/04/2022
Document Table of Contents Clocked Video Output and SDI II TX Interface

The clocked video interface from the CVO II IP core expects the SDI II TX core to pull data and its attributes by asserting the CVO II IP core's read enable signal (sdi_cvo_rden).
Figure 13. Clocked Video Output II with SDI II TX Interface Timing Diagram
Figure 14. Clocked Video Output II with SDI II TX Interface Block Diagram

The rate that the SDI II TX core uses to pull the data depends on the SDI standard. The table below describes the officially supported cadences.

Note: The IP core does not support SD-SDI (20 bits) mode for multi-rate designs with SDI Resampler.
Table 9.  sdi_cvo_rden (tx_dataout_valid) Cadence
SDI Standard tx_dataout_valid Cadence from SDI II TX Core
SD-SDI (10 bit) 1H 4L 1H 5L
SD-SDI (20 bit) 1H 10L
3G-SDI Always H
6G-SDI Always H
12G-SDI Always H