1. About the Video and Image Processing Suite
2. Avalon Streaming Video
3. Clocked Video
4. VIP Run-Time Control
5. Getting Started
6. VIP Connectivity Interfacing
7. Clocked Video Interface IPs
8. 2D FIR II IP Core
9. Mixer II IP Core
10. Clipper II IP Core
11. Color Plane Sequencer II IP Core
12. Color Space Converter II IP Core
13. Chroma Resampler II IP Core
14. Control Synchronizer IP Core
15. Deinterlacer II IP Core
16. Frame Buffer II IP Core
17. Gamma Corrector II IP Core
18. Configurable Guard Bands IP Core
19. Interlacer II IP Core
20. Scaler II IP Core
21. Switch II IP Core
22. Test Pattern Generator II IP Core
23. Trace System IP Core
24. Warp Lite Intel FPGA IP
25. Avalon-ST Video Stream Cleaner IP Core
26. Avalon-ST Video Monitor IP Core
27. VIP IP Core Software Control
28. Security Considerations
29. Video and Image Processing Suite User Guide Archives
30. Document Revision History for the Video and Image Processing Suite User Guide
A. Avalon-ST Video Verification IP Suite
7.1. Supported Features for Clocked Video Output II IP
7.2. Control Port
7.3. Clocked Video Input IP Format Detection
7.4. Clocked Video Output IP Video Modes
7.5. Clocked Video Output II Latency Mode
7.6. Generator Lock
7.7. Underflow and Overflow
7.8. Timing Constraints
7.9. Handling Ancillary Packets
7.10. Modules for Clocked Video Input II IP Core
7.11. Clocked Video Input II Signals, Parameters, and Registers
7.12. Clocked Video Output II Signals, Parameters, and Registers
15.1. Deinterlacing Algorithm Options
15.2. Deinterlacing Algorithms
15.3. Run-time Control
15.4. Pass-Through Mode for Progressive Frames
15.5. Cadence Detection (Motion Adaptive Deinterlacing Only)
15.6. Avalon-MM Interface to Memory
15.7. Motion Adaptive Mode Bandwidth Requirements
15.8. Avalon-ST Video Support
15.9. 4K Video Passthrough Support
15.10. Behavior When Unexpected Fields are Received
15.11. Handling of Avalon-ST Video Control Packets
15.12. Deinterlacer II Parameter Settings
15.13. Deinterlacing Control Registers
A.3.1. c_av_st_video_control
A.3.2. c_av_st_video_data
A.3.3. c_av_st_video_file_io
A.3.4. c_av_st_video_item
A.3.5. c_av_st_video_source_sink_base
A.3.6. c_av_st_video_sink_bfm_’SINK
A.3.7. c_av_st_video_source_bfm_’SOURCE
A.3.8. c_av_st_video_user_packet
A.3.9. c_pixel
A.3.10. av_mm_transaction
A.3.11. av_mm_master_bfm_`MASTER_NAME
A.3.12. av_mm_slave_bfm_`SLAVE_NAME
A.3.13. av_mm_control_register
A.3.14. av_mm_control_base
6.1.1. Interfacing with High-Definition Multimedia Interface (HDMI)
The order that the HDMI core presents chroma samples differs from the Avalon-ST expectations for YCbCr 4:4:4 and 4:2:2 sampling schemes.
Figure 24. Intel HDMI IP Core Chroma Sampling
For YCbCr 4:4:4, it is necessary to perform the translation shown in the figure below to meet the Avalon-ST requirements. If the system only handles YCbCr, then you can use the Color Plane Sequencer II IP core to perform this remapping. If the system handles both RGB and YCbCr, then you need to use the Color Space Converter II IP core to convert between RGB and YCbCr and also to remap the color plane ordering for YCbCr 4:4:4.
Figure 25. Remapping HDMI 4:4:4 to Avalon-ST Video 4:4:4
YCbCr 4:2:2 require two potential remappings. Symbols 2 and 1 carry the upper 8 bits of the chroma and luma samples. If the system supports 10- or 12-bit depth, the additional bits are carried together in symbol 0. To support 10 or 12 bit, YCbCr 4:2:2 requires the recombining of these lower bits with the upper bits in 2 distinct symbols as shown in the figure below.
Figure 26. Remapping HDMI YCbCr 4:2:2 to Avalon-ST YCbCr 4:2:2
At present, a Mux instantiated between the HDMI IP core and the clocked video IP core implements the recombining of the 4:2:2 MSBs with LSBs. Future clocked video IP cores will support this remapping internally.
Note: For 8-bit inputs, recombination is not necessary.
The positioning of the luma and chroma in the upper 2 symbols is at odds with the Avalon-ST requirement for the chroma in the bottom symbol and luma in the symbol above. The luma samples are in the correct place but the chroma samples must be remapped from the upper symbol to lower symbol.
If the system only handles YCbCr, then you can use the Color Plane Sequencer II IP core to remap the symbols. If the system handles both RGB and YCbCr, then you need to use the Color Space Converter II IP core to remap the chroma samples.