Video and Image Processing Suite User Guide

ID 683416
Date 4/04/2022
Public
Document Table of Contents

15.13. Deinterlacing Control Registers

Deinterlacer II Control Register Maps

The tables below describe the Deinterlacer II IP core control register map for run-time control. The Deinterlacer II reads the control data once at the start of each frame and buffers the data inside the IP core. The registers may safely update during the processing of a frame. Use these registers in software to obtain the best deinterlacing quality.

Table 49.  Deinterlacer II Control Register Map for Vertical Interpolation (Bob) and Field Weaving (Weave) Deinterlacing Algorithms
Address Register RO/RW Description
0 Control RW Bit 0 of this register is the Go bit, all other bits are unused.

Setting this bit to 0 causes the Deinterlacer II IP core to stop the next time that control information is read.

When you enable run-time control, the Go bit gets deasserted by default. If you do not enable run-time control, the Go is asserted by default.

Power on value: 0

1 Status RO Bit 0 of this register is the Status bit, all other bits are unused.
  • The Deinterlacer II IP core sets this address to 0 between frames when the Go bit is set to 0.
  • The Deinterlacer II IP core sets this address to 1 while the core is processing data and cannot be stopped.

Power on value: 0

2 Reserved This register is reserved for future use.

For motion-adaptive configurations, Intel recommends that you initially retain all values at their reset value, with the exception of the following:

  • The Motion Shift and Motion Scale registers may require adjustments to correct for weave artifacts caused by insufficient motion sensitivity. Refer to Tuning Motion Shift and Motion Scale Registers for more information.
  • The cadence-related registers in Set A (primarily registers 8 and 9) may require adjustments to correct undetected cadences.

The tables below detail the run-time control registers for the motion adaptive configurations of the Deinterlacer II IP core. Configurations with video-over-film mode enabled use Set B registers, all other configurations use Set A registers.

Note: For Set A registers, if you have not configured the Cadence detection and reverse pulldown parameter, the cadence-related registers have no effect.
Table 50.  Deinterlacer II Control Register Map for Motion-Adaptive Parameterizations Set A
Address Register RO/RW/WO Width Description
0 Go RW 32

Setting this bit to 0 causes the Deinterlacer II IP core to stop the next time that control information is read.

When you enable run-time control, the Go bit gets deasserted by default. If you do not enable run-time control, the Go is asserted by default.

Power on value: 0

1 Status RO 32
  • The Deinterlacer II IP core sets this address to 0 between frames when the Go bit is set to 0.
  • The Deinterlacer II IP core sets this address to 1 while the core is processing data and cannot be stopped.

Power on value: 0

2 Reserved This register is reserved for future use.
3 Unused Unused
4 3:2 Cadence Diff Count WO 8

If the IP core could not detect 3:2 cadences, poll this register to facilitate the tuning of 3:2 detection.

For example:
while(1){
    pollCount++;
    if (pollCount%350 == 0) {
        diffCount = IORD(VIP_DIL_BASE, 4);
        printf ("Dil diffCount = %0d\n", diffCount);}
The register returns the number of lines in the current field for which a difference is detected compared to the preceding field. A successfully detected 3:2 cadence generates output such as the following:
Dil diffCount = 253
Dil diffCount = 253
Dil diffCount = 0
Dil diffCount = 248
Dil diffCount = 249
Dil diffCount = 244
Dil diffCount = 245
Dil diffCount = 0
Dil diffCount = 240
Dil diffCount = 241
Dil diffCount = 237
Dil diffCount = 239
Dil diffCount = 0
Dil diffCount = 236
Dil diffCount = 235
Dil diffCount = 233

You are required to experiment with the polling rate to poll at a rate of approximately once per field.

5 3:2 Cadence Lock Threshold WO 8

The higher the threshold value, the more stringent the requirements for the deinterlacer to start performing reverse telecine deinterlacing. You may set lower threshold values for greater sensitivity to cadenced sequences. The default value is 6.

6 3:2 Cadence Unlock Threshold WO 8

Set this register lower than the 3:2 Cadence Lock Threshold register. The closer the value is to the 3:2 Cadence Lock Threshold register, the less stringent the requirements for the deinterlacer to lose lock and stop performing reverse telecine deinterlacing. The default value is 4.

7 3:2 Cadence Diff Threshold WO 8

The 3:2 Cadence Diff Count register increments when the “score” from the cadence detector for a line is equal or more than the 3:2 Cadence Diff Threshold register. The default value is 16.

8 3:2 Cadence Diff Line Ratio WO 8

This register affects the proportion of lines within a field that are required to exhibit a cadence before a 3:2 cadence lock can be achieved. Shift the number of lines using this value:

Lines >> 3:2 Cadence Diff Threshold

The default value is 4.

9 3:2 Cadence Diff Noise Suppresion WO 8

Use this register to shift the result of difference calculation logic which is used to determine whether a line is being repeated:

Diff result >> 3:2 Cadence Diff Noice Suppresion

The default value is 5 to allow resilience against noise in the LSBs masking a cadence relationship.

10 2:2 Cadence Lock Threshold WO 4

The higher the threshold value, the more stringent the requirements for the deinterlacer to start performing reverse telecine deinterlacing.

11 2:2 Cadence Unlock Threshold WO 4

Set this register lower than the 2:2 Cadence Lock Threshold register. The closer the value is to the 2:2 Cadence Lock Threshold register, the less stringent the requirements for the deinterlacer to lose lock and stop performing reverse telecine deinterlacing. The default value is 4.

12 2:2 Cadence Comb Threshold WO 8

A "comb count" for a field increments when the "score" from the 2:2 cadence detector for a line is ≥ 2:2 Cadence Comb Threshold. Its reset value is 16. Decrease this value to increase the deinterlacer's sensitivity to 22 cadences.

13 Unused Unused
14 Motion Shift WO 8

Specifies the amount of raw motion (SAD) data that is right-shifted. Shifting is used to reduce sensitivity to noise when calculating motion (SAD) data for both "bob" and "weave" decisions and cadence detection.

Note: It is very important to set this register correctly for good deinterlacing performance.

Tune this register in conjunction with the motion visualization feature. Higher values decrease sensitivity to noise when calculating motion, but may start to introduce weave artifacts if the value used is too high.

15 Unused Unused
16 Visualize Motion Values WO 3
  • Set bit 0 (Visualize Motion Values) to color pixels where motion is detected with pink for debugging purposes. The greater the luminance of the color pink, the more motion is detected.
  • Set bit 1 (Bob-Only Mode) to temporarily force the deinterlacer to do a pure "bob" deinterlace regardless of motion.
  • Set bit 2 (Weave-Only Mode) to temporarily force the deinterlacer to do a pure "weave" deinterlace regardless of motion.
Table 51.  Deinterlacer II Control Register Map for Motion-Adaptive with Video Over Film Parameterizations Set B
Address Register RO/RW/WO Width Description
0 Control RW 32

Bit 0 of this register is the Go bit, all other bits are unused.

Setting this bit to 0 causes the Deinterlacer II IP core to stop the next time that control information is read.

When you enable run-time control, the Go bit gets deasserted by default. If you do not enable run-time control, the Go is asserted by default.

Power on value: 0

1 Status RO 32

Bit 0 of this register is the Status bit, all other bits are unused.

  • The Deinterlacer II IP core sets this address to 0 between frames when the Go bit is set to 0.
  • The Deinterlacer II IP core sets this address to 1 while the core is processing data and cannot be stopped.

Power on value: 0

2 Reserved This register is reserved for future use.
3 Cadence Detected RO 1
  • When polled, the least significant bit (LSB) to 1, indicates the Deinterlacer II IP core has detected a 3:3 or 2:2 cadence and is performing reverse telecine.
  • Bit 0 indicates otherwise.

Range: 0–1

Power on value: 0

4 Extra Status RO 32
  • Bits [1:0]: 0 = Interlaced, 1 = Weave_current, 2 = Weave_future, 3 = Unused
  • Bit 2: VOF Lock Delay Up. The IP core sets this bit when the VOF lock delay period is over.
  • Bit 3: Adequate VOF region is detected.
  • Bit 4: Cadence 22 mode. The IP cores sets this bit when in 2:2 mode.
5 3:2 Cadence Film Pixels locked RO 32 Number of pixels displaying film content in a given field.

Range: 0–(232–1)

Power on value: 0

6 Motion in field RO 32 Total motion detected in the current field, computed from the sum of absolute differences (SAD) in Luma to the previous field of the same type, plus the Luma SAD of the previous field, and the next field, divided by 16.

Range: 0–(232–1)

Power on value: 0

7 3:2 Cadence VOF Histogram Total Phase 1 RO 32 Histogram of locked pixels, that is used for debugging purposes before the VOF lock. Indicates the number of pixels showing the presence of a potential cadence for this phase. If one phasing shows more pixels with a cadence present compared to other phasing by a factor 4 or more, all pixels in the field will be locked. Reverse telecine on per-pixel basis will commence VOF Lock Delay fields after the lock.

Range: 0–(232–1)

Power on value: 0

8 3:2 Cadence VOF Histogram Total Phase 2 32
9 3:2 Cadence VOF Histogram Total Phase 3 32
10 3:2 Cadence VOF Histogram Total Phase 4 32
11 3:2 Cadence VOF Histogram Total Phase 5 32
12 Cadence Detect and advanced tuning registers On RW 1

This register enables the cadence detection feature and (if configured) the video over film feature together with all the motion and cadence/VOF tuning registers.

  • Setting the LSB of this register to 1 enables cadence detection and tuning registers.
  • Setting the LSB of this register to 0 disables cadence detection and tuning registers.
  • Cadence detection is disabled on reset.

Range: 0–1

Power on value: 0

13 Video Threshold RW 8 The most important register to tune the video over film features. Set lower values for more emphasis on video and higher values for more emphasis on film. Set dynamically in software when the input content changes for best results.

Range: 0–255

Power on value: 255

14 Film Lock Threshold RW 24
  • Bits 2:0 - Lock threshold for 3:2 cadence detection
  • Bits 10:8 - Lock threshold for 2:2 cadence detection
  • Bits 23:16 - Comb threshold for 2:2 cadence detection

Other bits are unused.

Range:
  • Lock thresholds = 3–7
  • Comb threshold = 4–255
The higher the threshold values, the more stringent the requirements for the deinterlacer:
  • to mark a pixel as locked and
  • to start performing reverse telecine deinterlacing
You may set lower threshold values for greater sensitivity to cadenced sequences. Intel recommends that you leave all values at their reset value, unless a change to sensitivity is required.
Power on value: 0x0010_0707
  • Lock thresholds = 7
  • Comb threshold = 16
15 Film Unlock Threshold RW 24
  • Bits 2:0 - Unlock threshold for 3:2 cadence detection
  • Bits 10:8 - Unlock threshold for 2:2 cadence detection
  • Bits 23:16 - Delta threshold for 2:2 cadence detection

Other bits are unused.

Range:
  • Unlock thresholds = 0–5 (must be set to a value lower than the equivalent lock threshold)
  • Delta threshold = 4–255
The greater the difference between the lock and unlock threshold values, the more stringent the requirements for the deinterlacer:
  • to mark a pixel as unlocked and
  • to stop performing inverse telecine deinterlacing
You may set a small difference in the threshold values for greater sensitivity to changes in cadenced sequences. Intel recommends that you leave all values to their reset value, unless a change to sensitivity is required.
Power on value: 0x0005_0
  • Unlock threshold for 3:2 cadence detection = 2
  • Unlock threshold for 2:2 cadence detection = 4
  • Delta threshold = 5
16 VOF Lock Delay RW 5 Specifies the number of fields elapsed after the core detects a cadence, but before reverse telecine begins. The delay allows for any video to drop out. If you set a value less than five, the core locks to cadence quicker but costs potential film artifacts.

Range: 0–31

Power on value: 5

17 Minimum Pixels Locked RW 32 Specifies the least number of pixels showing a cadence for lock to occur. Increase the value of this register if inverse telecine is being erroneously applied to scenes where telecine should not be present.

Range: 0–(232–1)

Power on value: 40000

Note: Use a higher value for 1080i compared to PAL or NSTC video.
18 Minimum Valid SAD Value RW 8 When considering whether pixels should remain locked, the SAD values less than this range are ignored. Set this value high to prevent film pixels from decaying over time if they do not show a strong 3:2 cadence.

Range: 0–255

Power on value: 255

19 Scene Change Motion Multiplier RW 8 The Deinterlacer II IP core's scene change detection algorithm detects any scene changes or edits regardless of whether any current cadence continues or is interrupted. Scene changes cause immediate loss and reacquisition of cadence lock, which allows for very smooth deinterlacing of even rapid scene changes.

The algorithm detects scene changes based on a set of motion deltas between adjacent fields. The algorithm uses a multiplier in this calculation. This register sets the value of this multiplier, with a default value of 5 corresponding to a 4× motion delta between adjacent scenes. You may set other values as shown in Scene Change Motion Multiplier Value.

Range: 0–9

Power on value: 5

20 Minimum Film to Closed Caption Ratio RW 32 The Deinterlacer II IP core determines cadence for each pixel based on its immediate surroundings. For some standard definition content, film pixels may drop into video deinterlacing mode due to insufficient cadence signal. When the pixels go into video deinterlacing mode, you may set a minimum film to closed caption ratio.

The deinterlacer compares a count of pixels identified as film content in a reference area, with a count of those identified as film content in likely closed caption area. The deinterlacer only enters full video over film mode if the ratio of film content in the reference area to the closed caption area exceeds the threshold value.

This register sets the following threshold values:
Minimum Film to Closed Caption Register Minimum Ratio to Switch into Video Over Film Mode
0 1 (no effect)
1 4
2 16
3 64
4 256
5 1024

Range: 0–5

Power on value: 0

21 Minimum Pixel Kernel SAD for Field Repeats RW 8 Once a video achieves cadence lock, every pixel in the frame will either maintain or lose lock independently from then on. If the SAD value is less than the value for this register, then its lock count will be incremented. If it is higher than this value, its lock count will either remain unchanged or be decremented (if less than min valid SAD value).

Range: 0–255

Power on value: 200

22 History Minimum Value RW 3

The cadence bias for a given pixel.

  • Setting a lower value biases the pixels toward film.
  • Setting a higher value biases the pixels toward video.

The pixel SAD values are scaled according to the recent history that gives the frames an affinity for their historical state.

Range: 0–3

Power on value: 0

23 History Maximum Value RW 3

The cadence bias for a given pixel.

  • Setting a lower value biases the pixels toward film.
  • Setting a higher value biases the pixels toward video.
  • The value for this register must be higher than the value for the History Minimum Value register.

Range: 3–7

Power on value: 7

24 SAD Mask RW 10 When detecting cadences, the SAD values are AND’ed with this value. This value allows the LSBs to be masked off to provide protection from noise.

For example, use binary 11_1111_0000 to ignore the lower 4 bits of the SAD data when detecting cadences. This register works orthogonally from the Motion Shift register (Offset 25), which affects both motion calculation in general AND cadence detection.

Range: 512–1023

Power on value: 1008 (binary 1111110000)

25 Motion Shift RW 4 Specifies the amount of raw motion (SAD) data that is right-shifted. Shifting is used to reduce sensitivity to noise when calculating motion (SAD) data for both bob and weave decisions and cadence detection.
Note: It is very important to set this register correctly for good deinterlacing performance.

Tune this register in conjunction with the motion visualization feature. Higher values decrease sensitivity to noise when calculating motion, but may start to introduce weave artifacts if the value used is too high.

To improve video-over-film mode quality, consider using software to check the 3:2 Cadence State (VOF State) register, and to add one or two to the motion shift register's value when deinterlacing cadenced content.

Range: 0–7

Power on value: 3

Refer to Tuning Motion Shift and Motion Scale Registers for more information.
26 Visualize Film Pixels RW 1 Specifies the film pixels in the current field to be colored green for debugging purposes. Use this register in conjunction with the various VOF tuning registers.

Range: 0–1

Power on value: 0

27 Visualize Motion Values RW 1 Specifies the motion values for pixels represented with pink for debugging purposes. The greater the luminance of pink, the more motion is detected.

Range: 0–1

Power on value: 0

28 Reserved This register is reserved for future use.
29 Reserved This register is reserved for future use.
30 Motion Scale RW 8

An 8-bit quantity that is used to scale the effect of the detected motion. Refer to Tuning Motion Shift and Motion Scale Registers for more information.

The register scales the motion according to the following equation:

  • A value of 32 does not produce any scaling effect.
  • A value of 1 produces a scaling of 1/32.
  • A value of 255 produces a scaling of ×7.97

The lower the scaled motion value, the more weave the IP core performs. Therefore, if any weave artifacts are visible, increase this register value.

Power on value: 125 (corresponds to ×3.9)