Video and Image Processing Suite User Guide

ID 683416
Date 9/29/2022
Document Table of Contents

15.11. Handling of Avalon-ST Video Control Packets

In all parameterizations, the Deinterlacer II IP core generates a new and updated control packet just before the processed image data packet.

This packet contains the correct frame height and the proper interlace flag so that the following image data packet is interpreted correctly by the following IP cores.

Note: The Deinterlacer II IP core uses 0010 and 0011 to encode interlacing values into the generated Avalon-ST Video packets. These flags mark the output as being progressive and record information about the deinterlacing process, which can be used by other IP cores. For example, the Interlacer IP core uses this information to precisely extract the original interlaced fields from the deinterlaced frame. The interlacing is encoded as 0000 when the Deinterlacer II IP core passes a progressive frame through.

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