Visible to Intel only — GUID: bhc1411020436239
Ixiasoft
Visible to Intel only — GUID: bhc1411020436239
Ixiasoft
23.2. Trace System Signals
Signal | Direction | Description |
---|---|---|
clk_clk | Input | All signals on the trace system are synchronous to this clock. Do not insert clock crossing between the monitor and the trace system components. You must drive the trace monitors’ clocks from the same source which drives this signal. |
reset_reset | Output | This signal is asserted when the IP core is being reset by the debugging host. Connect this signal to the reset inputs on the trace monitors. Do not reset parts of the system being monitored with this signal because this will interfere with functionality of the system. |
usb_if_clk | Input | Clock provided by On-Board USB-Blaster II. All usb_if signals are synchronous to this clock; the trace system provides clock crossing internally. |
usb_if_reset_n | Input | Reset driven by On-Board USB-Blaster II. |
usb_if_full | Output | Host to the target full signal. |
usb_if_empty | Output | Target to the host empty signal. |
usb_if_wr_n | Input | Write enable to the host to target FIFO. |
usb_if_rd_n | Input | Read enable to the target to host FIFO. |
usb_if_oe_n | Input | Output enable for data signals. |
usb_if_data | Bidirectional | Shared data bus. |
usb_if_scl | Input | Management interface clock. |
usb_if_sda | Input | Management interface data. |
capturen_data | Input | capturen port Avalon-ST data bus. This bus enables the transfer of data out of the IP core. |
capturen_endofpacket | Input | capturen port Avalon-ST endofpacket signal. This signal marks the end of an Avalon-ST packet. |
capturen_empty | Input | capturen port Avalon-ST empty signal. |
capturen_ready | Output | capturen port Avalon-ST ready signal. The downstream device asserts this signal when it is able to receive data. |
capturen_startofpacket | Input | capturen port Avalon-ST startofpacket signal. This signal marks the start of an Avalon-ST packet. |
capturen_valid | Input | capturen port Avalon-ST valid signal. The IP core asserts this signal when it produces data. |
controln_address | Output | controln slave port Avalon-MM address bus. This bus specifies a byte address in the Avalon-MM address space. |
controln_burstcount | Output | controln slave port Avalon-MM burstcount signal. This signal specifies the number of transfers in each burst. |
controln_byteenable | Output | controln slave port Avalon-MM byteenable bus. |
controln_debugaccess | Output | controln slave port Avalon-MM debugaccess signal. |
controln_read | Output | controln slave port Avalon-MM read signal. The IP core asserts this signal to indicate read requests from the master to the system interconnect fabric. |
controln_readdata | Input | controln slave port Avalon-MM readdata bus. These input lines carry data for read transfers. |
controln_readdatavalid | Input | controln slave port Avalon-MM readdatavalid signal. The system interconnect fabric asserts this signal when the requested read data has arrived. |
controln_write | Output | controln slave port Avalon-MM write signal. The IP core asserts this signal to indicate write requests from the master to the system interconnect fabric. |
controln_writedata | Output | controln slave port Avalon-MM write signal. The IP core uses these input lines for write transfers. |
controln_waitrequest | Input | controln slave port Avalon-MM waitrequest signal. The system interconnect fabric asserts this signal to cause the master port to wait. |
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