Video and Image Processing Suite User Guide

ID 683416
Date 4/04/2022
Document Table of Contents

3.1.2. Embedded Synchronization Format: Clocked Video Input

The CVI IP cores support both 8 and 10-bit TRS and XYZ words.

When in 10-bit mode, the IP cores ignore the bottom 2 bits of the TRS and XYZ words to allow easy transition from an 8-bit system.

Table 10.  XYZ Word FormatThe XYZ word contains the synchronization information and the relevant bits of its format.
Bits 10-bit 8-bit Description


[5:0] [3:0] These bits are not inspected by the CVI IP cores.

H (sync)

6 4 When 1, the video is in a horizontal blanking period.

V (sync)

7 5 When 1, the video is in a vertical blanking period.

F (field)

8 6 When 1, the video is interlaced and in field 1. When 0, the video is either progressive or interlaced and in field 0.


9 7 These bits are not inspected by the CVI IP cores.

For the embedded synchronization format, the vid_datavalid signal indicates a valid BT656 or BT1120 sample. The CVI IP cores only read the vid_data signal when vid_datavalid is 1.

Figure 15. Vid_datavalid Timing

The CVI IP cores extract any ancillary packets from the Y channel during the vertical blanking. Ancillary packets are not extracted from the horizontal blanking.

  • Clocked Video Input IP core—The extracted packets are produced through the CVI IP core's Avalon-ST output with a packet type of 13 (0xD).
  • Clocked Video Input II IP core— The extracted packets are stored in a RAM in the IP core, which can be read through the control interface.