Video and Image Processing Suite User Guide

ID 683416
Date 4/04/2022
Public
Document Table of Contents

18.2. Configurable Guard Bands Control Registers

Table 59.  Configurable Guard Bands Register MapYou may choose to enable an Avalon-MM control slave interface for the Configurable Guard Bands IP core to enable run-time updating of the guard band values. As is the convention with all VIP IP cores, when a control slave interface is included, the IP core resets into a stopped state and must be started by writing a ‘1’ to the Go bit of the control register before any input data is processed.
Address Register Description
0 Control Bit 0 of this register is the Go bit. All other bits are unused. Setting this bit to 0 causes the IP core to stop at the end of the next frame/field packet.

When you enable run-time control, the Go bit gets deasserted by default. If you do not enable run-time control, the Go is asserted by default.

1 Status Bit 0 of this register is the Status bit, all other bits are unused. The IP core sets this address to 0 between frames. The IP core sets this address to 1 when it is processing data and cannot be stopped.
2 Interrupt This bit is not used because the IP core does not generate any interrupts.
3 Lower guard band 0 Value for lower guard band for color 0.
4 Upper guard band 0 Value for upper guard band for color 0.
5 Lower guard band 1 Value for lower guard band for color 1.
6 Upper guard band 1 Value for upper guard band for color 1.
7 Lower guard band 2 Value for lower guard band for color 2.
8 Upper guard band 2 Value for upper guard band for color 2.
9 Lower guard band 3 Value for lower guard band for color 3.
10 Upper guard band 3 Value for upper guard band for color 3.