1. About the Video and Image Processing Suite
|Intel® Quartus® Prime Design Suite 22.1|
The Intel® Video and Image Processing (VIP) Suite is available in the DSP library of the Intel® Quartus® Prime software. You can configure the IPs to the required number of bits per symbols, symbols per pixel, symbols in sequence or parallel, and pixels in parallel.
The VIP Suite offers the following IPs:
- 2D FIR II Intel® FPGA IP
- Avalon-ST Video Monitor Intel® FPGA IP (Available only in Platform Designer (Standard) edition)
- Avalon-ST Video Stream Cleaner Intel® FPGA IP
- Chroma Resampler II Intel® FPGA IP
- Clipper II Intel® FPGA IP
- Clocked Video Input II Intel® FPGA IP
- Clocked Video Output II Intel® FPGA IP
- Color Plane Sequencer II Intel® FPGA IP
- Color Space Converter II Intel® FPGA IP
- Configurable Guard Bands Intel® FPGA IP
- Control Synchronizer Intel® FPGA IP (Available only in Platform Designer (Standard) edition)
- Deinterlacer II Intel® FPGA IP
- Frame Buffer II Intel® FPGA IP
- Gamma Corrector II Intel® FPGA IP
- Interlacer II Intel® FPGA IP
- Mixer II Intel® FPGA IP
- Scaler II Intel® FPGA IP
- Switch II Intel® FPGA IP
- Test Pattern Generator II Intel® FPGA IP
- Trace System Intel® FPGA IP (Available only in Platform Designer (Standard) edition)
- Warp Lite IP
These IPs transmit and receive video according to the Avalon streaming video standard. Most IPs receive and transmit video data according to the same Avalon streaming video configuration, but some explicitly convert from one Avalon streaming video configuration to another. For example, you can use the Color Plane Sequencer II IP to convert from 1 pixel in parallel to 4.
All VIP IPs require even frame widths when using 4:2:2 data; odd frame widths create unpredictable results or distorted images. The Clipper II IP requires even clip start offsets and the Mixer II IP requires even offsets when using 4:2:2 data.
The signal names are standard Avalon streaming signals, and so by default, not enumerated. Some IPs may have additional signals.
All IPs in the VIP Suite support pixels in parallel, with the exception of Control Synchronizer, and Avalon-ST Video Monitor IP. Most of the IPs support 8 pixels in parallel and 8K resolutions.
|VIP IP Cores||Minimum Input and Output Resolution in Pixels (Width × Height)||Maximum Input and Output Resolution in Pixels (Width × Height)|
|Clocked Video Input II||32 × 32||8192 × 8192|
|Clocked Video Output II||32 × 32||8192 × 8192|
|Control Synchronizer||32 × 32||1920 × 1080|
|Deinterlacer II||32 × 32||4096 × 2160 1|
|Frame Buffer II (Frame Reader and Frame Writer)||32 × 32||7680 × 4320|
|Warp Lite IP||128 × 128||1920 × 1080|
|Other IP||32 × 32||8192 × 8192|
Device Family Support
In-System Performance and Resource Guidance
Stall Behavior and Error Recovery
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