Video and Image Processing Suite User Guide

ID 683416
Date 4/04/2022
Public
Document Table of Contents

26.4. Avalon-ST Video Monitor Control Registers

Table 87.  Avalon-ST Video Monitor Register Map
Address Register Description
0 Identity Read only register—manufacturer and monitor identities.
  • Bits 11:0 are identities for the manufacturer, Intel = 0×6E
  • Bits 27:12 are identities for the monitor, Avalon-ST video monitor = 0×110
1 Configuration Information For use of System Console only.
2 Configuration Information For use of System Console only.
3 Configuration Information For use of System Console only.
4 Control
  • Setting bits 0 and 8 to 1 sends statistic counters.
  • Setting bits 0 and 9 to 1 sends up to first 6 beats on the Avalon-ST data bus.
  • Setting bit 0 to 0 disables both the statistics and beats.
5 Control
  • Bits 15:0 control the linear feedback shift register (LFSR) mask for the pixel capture randomness function. The larger the mask, the less randomness is used to calculate the position of the next pixel to sample.
  • Bits 31:16 control the minimum gap between sampled pixels. The larger the gap, the more constant is applied to calculate the position of the next pixel.