Video and Image Processing Suite User Guide

ID 683416
Date 9/29/2022
Document Table of Contents

7.4. Clocked Video Output IP Video Modes

The video frame is described using the mode registers that you access through the Avalon memory-mapped control port.

If you turn off Use control port in the parameter editor for the IP, the output video format always has the format specified in the parameter editor.

You can configure the IP to support between 1 to 13 different modes and each mode has a bank of registers that describe the output frame.

When the IP receives a new control packet on the Avalon streaming video input, it searches the mode registers for a mode that is valid. The valid mode must have a field width and height that matches the width and height in the control packet.

The Video Mode Match register shows the selected mode:

  • If the IP finds a matching mode, it completes the current frame; duplicating data if needed before commencing output with the new settings at the beginning of the next frame.
  • If the IP does not find a matching mode, the video output format is unchanged.

If a new control packet is encountered before the expected end of frame, the IP completes the timing of the current frame with the remaining pixels taking the value of the last pixel output. The IP changes modes to the new packet at the end of this frame, unless you enable the Low Latency mode. During this period, when the FIFO buffer fills, the IP back-pressures the input until it is ready to transmit the new frame.

You must enable the Go bit to program the mode control registers. The sync signals, controlled by the mode control registers, reside in the video clock domain. The register control interface resides in the streaming clock domain. Enabling the Go bit, indicating that both clocks are running, avoids situations where a write in the streaming side cannot be issued to the video clock side because the video clock isn't running.

Figure 38. Progressive Frame ParametersThe figure shows how the register values map to the progressive frame format.

Figure 39. Interlaced Frame ParametersThe figure shows how the register values map to the interlaced frame format.

You can only write to the mode register of a mode bank if that mode is marked as invalid. To reconfigure mode 1:

  1. Write 1 to the Bank Select register.
  2. Write 0 to the Mode N Valid configuration register.
  3. Write to the Mode N configuration registers, the Clocked Video Output II IP mirrors these writes internally to the selected bank.
  4. Write 1 to the Mode N Valid register. The mode is now valid and you can select it.

You can configure a currently-selected mode in this way without affecting the video output of the IP.

If multiple modes match the resolution, the function selects the lowest mode. For example, the function selects Mode1 over Mode2 if both modes match. To allow the function to select Mode2, invalidate Mode1 by writing a 0 to its mode valid register. Invalidating a mode does not clear its configuration.

Figure 40. Mode Bank Selection

Did you find the information on this page useful?

Characters remaining:

Feedback Message