- Updated support for Intel® Cyclone® 10 LP and Intel® Cyclone® 10 GX devices as final.
- Changed the term Qsys to Platform Designer.
- Made extensive changes to the Avalon-ST Video Verification IP Suite section based on the changes in the Intel® Quartus® Prime software.
- Changed the minimum width and height values to 32 in the Clipper II Parameter Settings section.
- Added a note that if you have enabled run-time control, the Go bit gets deasserted by default for the following IP cores:
- 2D FIR Filter II
- Clipper II
- Deinterlacer II
- Scaler II
- Frame Buffer II
- Configurable Guard Bands
- Interlacer II
- Scaler II
- Test Pattern Generator II
- Added a note that the following IP cores require even frame widths when using 4:2:2 data; odd frames widths create unpredictable results or distorted images:
- 2D FIR Filter II
- Deinterlacer II
- Scaler II
- Configurable Guard Bands
- Scaler II
- Mixer II
- Test Pattern Generator II
- Added information that if new frame dimensions are set, the Frame Buffer II IP core requires a write to the Frame Start Address register for the new settings to take effect.
- Added new parameters for Frame Buffer II IP core:
- Delay length (frames)
- Drop/repeat user packets
- Edited the Reduced control register readback parameter information for the Gamma Corrector IP core that only values written to registers 5 and 6 in the control slave interface can be read back. Contents of registers 6 and above cannot be read back in any mode.
- Added a note in the Gamma Corrector Control Registers section that the values written to registers 6 and above cannot be read back in any mode.
- Updated the Memory Map for Frame Reader section with information about ancillary packets and edited the Memory Map for Base Address 0x1000_0000 for Non 8-Bit Pixel Values figure with the correct mapping.
- Updated the Clocked Video Output II Control Registers section. Some minor changes were made to the common control registers to correct reported bugs and limitations.
- Added a new register (Motion scale) to the Deinterlacer II Control Registers section.
- Added information and changed the title of the Tuning Motion Shift section to .
||Republished to add some missing chapters due to technical glitch.
- Rebranded as Intel.
- Added preliminary device support for Intel® Cyclone® 10 LP and Intel® Cyclone® 10 GX devices.
- Removed all information about the following IP cores. These IP cores are no longer supported in Intel® Quartus® Prime versions 17.0 and later.
- 2D FIR Filter
- Alpha Blending Mixer
- Chroma Resampler
- Color Space Converter
- Color Plane Sequencer
- Frame Buffer
- Frame Reader
- Gamma Corrector
- Added information for the Configurable Guard Bands IP core. This is a new IP core being released in version 17.0.
- Updated the performance and resource data information based on an Arria 10 device.
- Updated the stall behavior and error recovery information for 2D FIR Filter II, CVO/CVO II, Color Plane Sequencer II, and Deinterlacer II IP cores.
- Added or updated these chapters:
- Clocked Video
- VIP Run-Time Control
- VIP Connectivity Interfacing
- VIP Software Control
- Reorganized the signals, parameters, and registers information according to the respective Clocked Video Interface IP cores.
- Updated the description for the vid_color_encoding and vid_bit_width signals in the CVI II IP core. Tie these signals to low if no equivalent signals are available from the IP core driving the CVI II.
- Updated GUI information for the Chroma Resampler II IP core. Added the following parameters:
- Enable vertical luma adaptive resampling
- Vertical chroma siting
- Variable 3 color interface
- Enable 4:2:0 input
- Enable 4:2:0 output
- Updated GUI information for the Deinterlacer II IP core.
- Removed the How user packets are handled: Pass all user packets through to the output and Enable embedded chroma resamplers parameters.
- Edited the description for the Deinterlacing algorithm, Fields buffered prior to output, and Use separate clock for the Avalon-MM master interface(s) parameters.
- Changed Cadence Detect On register to Cadence Detect and advanced tuning registers On register for the Deinterlacer II IP core. This updated register enables the cadence detection feature and (if configured) the video over film feature together with all the motion and cadence/VOF tuning registers.
- Updated the Scaler II calculation for the nearest neighbor algorithm.
- Removed edge sharpening feature for the Scaler II IP core.
- Clarified the GUI information for the Test Pattern Generator II IP core.
- Added information about these new IP cores:
- 2D FIR Filter II
- Chroma Resampler II
- Color Plane Sequencer II
- Gamma Corrector II
- Interlacer II
- Added a flowchart to illustrate the behavior of the VIP IP cores.
- Updated information for Deinterlacer II IP core (this IP core is now merged with the Broadcast Deinterlacer IP core).
- Updated the Deinterlacer II parameter settings table to include the new parameters.
- Added new information about Avalon-ST Video and 4K Video passthrough support.
- Updated the Motion Adaptive mode bandwidth requirements to reflect the upgraded Deinterlacer II IP core.
- Updated information for Clocked Video Output IP cores.
- Updated mode bank selection information for CVO and CVO II IP cores. You can configure the IP cores to support 1 to 13 modes.
- Added information to enable the Go bit for both CVO IP cores to avoid situations where a write in the streaming side cannot be issued to the video clock side because the video clock isn't running.
- Added new parameter for CVO II IP core: Low latency mode. Setting this parameter to 1 enables the IP core to start timing for a new frame immediately
- Updated information for Clocked Video Input II IP core.
- Added three new parameters: Enable matching data packet to control by clipping, Enable matching data packet to control by padding, Overflow handling.
- Added two new signals: Clipping and Padding.
- Updated description for these signals: vid_color_encoding and vid_bit_width.
- Updated information about the Status register. The register now includes bits to support clipping and padding features.
- Updated information for Mixer II IP core.
- Updated alpha stream information for Mixer II IP core. When you enable alpha stream, the LSB is in Alpha value and the control packets are composed of all symbols including Alpha.
- Corrected the description for the Control and Status registers.
- Added information about a new IP core: Avalon-ST Video Stream Cleaner.
- Frame Buffer II IP core:
- Added new Frame Buffer II IP core parameters:
- Enable use of fixed inter-buffer offset
- Inter-buffer offset
- Module is Frame Reader only
- Module is Frame Writer only
- Updated the default values for these Frame Buffer II IP core parameters:
- Maximum frame width = 1920
- Maximum frame height = 1080
- Updated the existing and added new Frame Buffer II IP core registers.
- Added new information for Frame writer-only and Frame reader-only modes.
- Broadcast Deinterlacer IP core:
- Updated the existing and added new Broadcast Deinterlacer IP core registers.
- Edited the Design Guidelines for Broadcast Deinterlacer IP Core section and removed the Active Video Threshold Adjustment section. The information is no longer relevant.
- Clocked Video Interface IP core:
- Added new or updated these Clocked Video Input II IP core signals:
- vid_locked (updated)
- vid_datavalid (updated)
- Added a new register, Color Pattern, for the Clocked Video Input II IP core.
- Updated information for the Standard format for the Clocked Video Input II IP core.
- Added new information for output video modes in the Clocked Video Output II IP core.
- Added information that multiple pixels in parallel are only supported for external sync mode in the Clocked Video Output II IP core.
- Removed the Accept synchronization outputs parameter and the related signals from the Clocked Video Output II IP core.
- Mixer II IP core:
- Added new or updated the following Mixer II IP core parameters:
- Number of inputs
- Alpha Blending Enable
- Layer Position Enable
- Register Avalon-ST ready signals
- Uniform values
- Number of pixels transmitted in 1 clock cycle
- Alpha Input Stream Enable
- 4:2:2 support
- How user packets are handled
- Removed these Mixer II IP core parameters:
- Number of color planes
- Run-time control
- Output format
- Updated the existing and added new Mixer II IP core registers.
- Added alpha blending information for Mixer II IP core in the Alpha Blending - Mixer II section.
- Added information about defining layer mapping in the Layer Mapping- Mixer II section.
- Switch II IP core:
- Updated the features information to include that each input drives multiple outputs and each output is driven by one input.
- Added a new register: Din Consume Mode Enable
- Added links to archived versions of the Video and Image Processing Suite User Guide.
- Removed information about the Clipper and Test Pattern Generator IP cores. These cores are no longer supported in versions 15.1 and later.
- Changed instances of Quartus II to Intel® Quartus® Prime .
- Edited the description of the vid_de signal for the Clocked Input II IP core—this signal is driven by the IP core to indicate the data lines are carrying active picture.
- Added two new Mixer II IP core registers.
- Added conditions for the Video Mixing IP cores; if these conditions are not met, then the Mixer behavior is undefined and the core is likely to lock up.
- Edited the description of the Coeff-commit control register for the Color Space Converter II IP core. Writing a 1 to this location commits the writing of coefficient data.
- Edited the description of the Input (0-3) Enable registers for the Mixer II IP core. The 1-bit registers are changed to 2-bit registers:
- Set to bit 0 of the registers to display input 0.
- Set to bit 1 of the registers to enable consume mode.
- Edited the description of the Interrupt register to unused for the Color Space Converter II, Frame Buffer II (writer), and Test Pattern Generator II IP cores.
- Edited the register information for the Switch II IP core:
- Changed the description of the Interrupt register to state that bit 0 is the interrupt status bit.
- Updated the description of the Control register to add that bit 1 of the register is the interrupt enable bit.
- Edited the typo in address 15 of the Switch II IP core— Dout12 Output Control changed to Dout11 Output Control.
- Edited the typos in the descriptions for Output Width and Output Height registers for the Test Pattern Generator IP cores.
- Edited the parameter settings information for the Mixer II IP core.
- Added description for new parameter Pattern which enables you to select the pattern for the background layer.
- Removed information about Color planes transmitted in parallel . This feature is now default and internally handled through the hardware TCL file.
- Edited the parameter settings information for the Frame Buffer II IP core.
- Added descriptions for parameters that were not supported in the previous version: Maximum ancillary packets per frame, Interlace support, Locked rate support, Run-time writer control, andRun-time reader control
- Removed information about Ready latency and Delay length (frames). These features are fixed to 1 and internally handled through the hardware TCL file.
- Edited the parameter settings information for the Avalon-ST Video Monitor IP core.
- Added description for new parameters: Color planes transmitted in parallel and Pixels in parallel.
- Removed information about the Number of color planes in sequence parameter. You can specify whether to transmit the planes in parallel or in series using the Color planes transmitted in parallel parameter.
- Added a note that the Capture video pixel data feature only functions if you specify the number of pixels transmitted in parallel to 1.
- Added support for Arria 10 and MAX 10 devices. Arria 10 devices support only the following IP cores: Avalon-ST Video Monitor, Broadcast Deinterlacer, Clipper II, Clocked Video Input, Clocked Video Input II, Clocked Video Output, Clocked Video Output II, Color Space Converter II, Deinterlacer II, Frame Buffer II, Mixer II, Scaler II, Switch II, and Test Pattern Generator II.
- Removed the Generate Display Port output parameter from the Clocked Video Output II IP core. This feature is now default and internally handled through the hardware TCL file.
- Added description for a new signal for Clocked Video Input II IP core: vid_hdmi_duplication[3:0].
- Added information for the missed out Coeff-commit control register for the Color Space Converter II IP core.
- Edited the description for the Frame Buffer II parameters.
- Added new IP cores: Clocked Video Output II, Clocked Video Input II, Color Space Converter II, Mixer II, Frame Buffer II, Switch II, and Test Pattern Generator II.
- Revised the performance and resource data for different configurations using Arria V and Cyclone V devices.
- Added information about IP catalog and removed information about MegaWizard Plug-In Manager.
- Updated bit 5 of the Status register as unused for the Clocked Video Input IP core.
- Corrected the formula for adjusting the filter function’s phase for the Scaler II IP core.
- Consolidated the latency information for all IP cores in the Overview chapter.
- Consolidated the stall behavior and error recovery information for all IP cores in the Overview chapter.
- Moved the 'Video Formats' section from Clocked Video Input and Output chapters to the Interfaces chapter.
- Added information on 4:2:2 support.
- Added Design Guidelines section for the Broadcast Deinterlacer IP core.
- Removed information about Arria GX, Cyclone, Cyclone II, Stratix, Stratix GX, Stratix II, Stratix II GX, and all HardCopy devices. Altera no longer supports these devices.
- Added new IP cores: Broadcast Deinterlacer and Clipper II
- Removed Scaler IP core. This core is no longer supported in version 13.0 and later.
- Added information about the Add data enable signal parameter and the vid_de signal for Clocked Video Input IP core.
||Added the following information for the Avalon-ST Video Monitor IP core.
- Added description for packet visualization.
- Added explanation for Capture Rate per 1000000 option for monitor settings.
- Added Capture video pixel data parameter.
- Added Control Bits entry to the register map.
- Added Deinterlacer II Sobel-Based HQ Mode information for the Deinterlacer II IP core.
- Updated Table 1–17 to include latest Deinterlacer II IP core performance figures for Cyclone IV and Stratix V devices.
- Edited the description of the rst signal for the Clocked Video Output IP core.
- Added a note to explain that addresses 4, 5, and 6 in the Frame Buffer control register map are optional and visible only when the GUI option is checked.
- Updated Table 23–4 to include the functionality of address 0 in the register map.
- Added new IP cores: Avalon-ST Video Monitor and Trace System.
- Added information on the edge-adaptive scaling algorithm feature for the Scaler II IP core.
- Reorganized the user guide.
- Added new appendixes: “Avalon-ST Video Verification IP Suite” and “Choosing the Correct Deinterlacer”.
- Updated Table 1-1 and Table 1-3.
- Added new IP core: Deinterlacer II.
- Added new polyphase calculation method for Scaler II IP core.
- Final support for Arria II GX, Arria II GZ, and Stratix V devices.
- Added new IP core: Scaler II.
- Updated the performance figures for Cyclone IV GX and Stratix V devices.
- Preliminary support for Stratix V devices.
- Added new IP core: Interlacer.
- Updated Clocked Video Output and Clocked Video Input IP cores to insert and extract ancillary packets.
- Added new IP cores: Frame Reader, Control Synchronizer, and Switch.
- The Frame Buffer IP core supports controlled frame dropping or repeating to keep the input and output frame rates locked together. The IP core also supports buffering of interlaced video streams.
- The Clipper, Frame Buffer, and Color Plane Sequencer IP cores now support four channels in parallel.
- The Deinterlacer IP core supports a new 4:2:2 motion-adaptive mode and an option to align read/write bursts on burst boundaries.
- The Line Buffer Compiler IP core has been obsoleted.
- The Interfaces chapter has been re-written.
- The Deinterlacer IP core supports controlled frame dropping or repeating to keep the input and output frame rates locked together.
- The Test Pattern Generator IP core can generate a user-specified constant color that can be used as a uniform background.
- Preliminary support for Arria II GX devices.