Video and Image Processing Suite User Guide

ID 683416
Date 4/04/2022
Document Table of Contents

6. VIP Connectivity Interfacing

Avalon-ST Video expects pixel subsamples to be arranged in particular orders, depending on the sampling method selected.

While the Color planes transmitted in parallel and Number of color planes parameters define an interface that is capable of carrying the sampling methods, they do not enforce the transmission of particular sub-samples in particular symbols of the Avalon-ST video packet.

You have to understand the arrangement of the color planes on entry to the pipeline and any reconfiguration of this order performed by the components within the pipeline. This is a particular concern around the connectivity points. The connectivity IP cores present data arranged according to their respective standards. When connected to a clocked video component, the clocked video components will package the data as it is presented to the IP core. They do not re-arrange it. In simple terms, on each clock cycle during the active video, the Clocked Video Input (CVI) II IP samples the entire data bus and divides the samples into pixels according to the Number of color planes, Bits per color plane, and Pixels in parallel parameters used to configure the module.

Figure 22. Variable Interpretation of Pixels on a Clocked Video Data Bus Based on Parameterization

If the configuration selected were PiP=1 and CP=4, but a 10-bit RGB signal were being fed on Data [29:30], the output pixels will still be 40 bits in size, the unused data bits having been sampled.

The converse function of the Clocked Video Output (CVO) II IP drives the entire data bus on each clock cycle. To drive 10-bit RGB on Data[29:0] in the PiP=1 and CP=4 configuration, the VIP pipeline would have to generate 40-bit pixels containing the 30 data bits and 10 null bits.