Video and Image Processing Suite User Guide

ID 683416
Date 4/04/2022
Document Table of Contents

7.9. Handling Ancillary Packets

The Clocked Video Interface IPs use active format description (AFD) extractor and inserter examples to handle ancillary packets.

Ancillary Packets (Clocked Video Input II IP)

When you turn on the Extract Ancillary Packets parameter in embedded sync mode, the Clocked Video Input IP extracts any ancillary packets that are present in the Y channel of the incoming video's vertical blanking. The ancillary packets are stripped of their TRS code and placed in a RAM. You can access these packets by reading from the Ancillary Packet register. The packets are packed end to end from their Data ID to their final user word.

The RAM is 16 bits wide—two 8-bit ancillary data words are packed at each address location. The first word is at bits 0–7 and the second word is at bits 8–15. A word of all 1's indicates that no further ancillary packets are present and can appear in either the first word position or the second word position.

Figure 41. Ancillary Packet RegisterThe figure shows the position of the ancillary packets. The different colors indicate different ancillary packets.

Use the Depth of ancillary memory parameter to control the depth of the ancillary RAM. If available space is insufficient for all the ancillary packets, excess packets will be lost. The IP fills the ancillary RAM from the lowest memory address to the highest during each vertical blanking period—the IP overwrites the packets from the previous blanking periods. To avoid missing ancillary packets, the ancillary RAM should be read every time the End of field/frame interrupt register triggers.

AFD Inserter (Clocked Video Output IP)

When the output of the AFD Inserter connects to the input of the Clocked Video Output IP, the AFD Inserter inserts an Avalon streaming video ancillary data packet into the stream after each control packet. The AFD Inserter sets the DID and SDID of the ancillary packet to make it an AFD packet (DID = 0x41, SDID = 0x5). The contents of the ancillary packet are controlled by the AFD Inserter register map.

You can get the AFD Extractor from <install_dir>\ip\altera\clocked_video_output\afd_example.

Table 20.  AFD Inserter Register Map
Address Register Description
0 Control
  • When bit 0 is 0, the core discards all packets.
  • When bit 0 is 1, the core passes through all non-ancillary packets.

1 Reserved.
2 Reserved.
3 AFD Bits 0-3 contain the active format description code.
4 AR Bit 0 contains the aspect ratio code.
5 Bar data flags Bits 0-3 contain the bar data flags to insert.
6 Bar data value 1 Bits 0-15 contain bar data value 1 to insert.
7 Bar data value 2 Bits 0-15 contain bar data value 2 to insert.
8 AFD valid
  • When bit 0 is 0, an AFD packet is not present for each image packet.
  • When bit 0 is 1, an AFD packet is present for each image packet.