Video and Image Processing Suite User Guide

ID 683416
Date 4/04/2022
Public
Document Table of Contents

A.2.1. Generating the Testbench Netlist

  1. Copy the verification files from $(QUARTUS_ROOTDIR)/../ip/altera/vip/verification to a local directory.
  2. Change the directory to where you copied the files to and ensure that write permissions exist on testbench/testbench.qsys and dut/dut.qsys so that the system can be saved prior to generation.
  3. Create an ipx file pointing to the DUT: >ip-make-ipx --source-directory=dut/
  4. Skip this step if you are using Intel® Quartus® Prime Standard Edition . If you use Intel® Quartus® Prime Pro Edition, create a new project in the Intel® Quartus® Prime software before you generate the testbench.
    1. Next, start the Platform Designer system integration tool (Qsys).
    2. To select the Platform Designer system, browse to testbench and select testbench.qsys.
    3. Click Open and OK to convert the project to the Intel® Quartus® Prime Pro Edition format.
  5. Skip this step if you are using Intel® Quartus® Prime Pro Edition . Start the Platform Designer system integration tool from the Intel® Quartus® Prime software (Tools > Platform Designer or through command line.
    >cd testbench
    >qsys-edit testbench.qsys
  6. The system refreshes and shows an example DUT. In this instance, the example DUT is another Platform Designer system comprised of the Mixer II and Frame Buffer II IP cores. You can easily replace this example by any other VIP IP cores or user IP functions. None of the interfaces are exported. All of the DUT Avalon-MM and Avalon-ST I/Os are attached to the BFM, which in turn interfaces to the class library.
    Figure 85.  Platform Designer Dialog Box
  7. Create the testbench.v netlist from the Platform Designer project by clicking Generate HDL, set Create simulation model to Verilog. Click Generate. Close the Generate completed dialog box, and exit the Platform Designer and Intel® Quartus® Prime software (if open).
    Platform Designer generates the testbench.v netlist and all the required simulation files.
    Note: Platform Designer in the Intel® Quartus® Prime Pro Edition software may report that some of the IP cores have validation errors. You can safely ignore this error.