AN 796: Cyclone® V and Arria® V SoC Device Design Guidelines

ID 683360
Date 3/30/2022
Document Table of Contents

3.4. HPS EMIF Design Considerations

A critical component of the HPS subsystem is the external SDRAM memory. For Cyclone® V and Arria® V SoC device, the HPS has a dedicated SDRAM Subsystem that interfaces with the HPS External Memory Interface I/O.

Review the following guidelines to properly design the interface between the memory and the HPS. These guidelines are essential to successfully connecting external SDRAM to the HPS.

The External Memory Interface Handbook, Volume 3: Reference Material includes the functional description of the HPS memory controller. The supported interface options are listed for DDR3, DDR2 and LPDDR2.