AN 796: Cyclone® V and Arria® V SoC Device Design Guidelines

ID 683360
Date 3/30/2022
Document Table of Contents
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4.2.2. Configuration

The Cyclone® V / Arria® V SoC devices support two main type sof configuration flows:
  • Traditional FPGA configuration
  • HPS-initiated FPGA configuration

HPS-initiated configuration uses fast passive parallel (FPP) mode allowing the HPS to configure the FPGA using storage locations accessible to the HPS such as QSPI, SD/MMC and NAND flash. The FPGA configuration flows for the Cyclone® V/ Arria® V SoC are the same for the Cyclone® V/ Arria® V FPGA devices where an external configuration data source is connected to the control block in the FPGA.