AN 796: Cyclone® V and Arria® V SoC Device Design Guidelines

ID 683360
Date 3/30/2022
Document Table of Contents

2.1. Guidelines for Interconnecting the HPS and FPGA

The memory-mapped connectivity between the HPS and the FPGA fabric is a crucial tool to maximize the performance of your design.

Design guidelines for the FPGA portion of your design are provided in the Arria V and Cyclone V Design Guidelines.