AN 796: Cyclone® V and Arria® V SoC Device Design Guidelines

ID 683360
Date 3/30/2022
Document Table of Contents

4.5.7. I2C Interface Design Guidelines

GUIDELINE: Instantiate the open-drain buffer when routing I2C signals through the FPGA fabric.

When routing I2C signals through the FPGA, note that the I2C pins from the HPS to the FPGA fabric (i2c*_out_data, i2c*_out_clk) are not open-drain and are logic level inverted. Thus, when you want to drive a logic level zero onto the I2C bus, these pins are high. This implementation is useful as they can be used to tie to an output enable of a tri-state buffer directly. You must use the altiobuf to implement the open-drain buffer.

GUIDELINE: Ensure that the pull-ups are added to the external SDA and SCL signals in the board design.

Because the I2C signals are open drain, pull-ups are required to make sure that the bus is pulled high when no device on the bus is pulling it low.

Figure 6. I2C Wiring to FPGA pins

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