AN 796: Cyclone® V and Arria® V SoC Device Design Guidelines

ID 683360
Date 3/30/2022
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4.5.6. UART Interface Design Guidelines

GUIDELINE: Properly connect flow control signals when routing the UART signals through the FPGA fabric.

When routing UART signals through the FPGA, the flow control signals are available. If flow control is not being used, connect the FPGA signals as shown in the following table.
Table 9.  UART Connections to Disable Flow Control

Signal

Direction

Connection

CTS

Input

Low

DSR

Input

High

DCD

Input

High

RI

Input

High

DTR

Output

No-connect

RTS

Output

No-connect

OUT1_N

Output

No-connect

OUT2_N

Output

No-connect