AN 796: Cyclone® V and Arria® V SoC Device Design Guidelines

ID 683360
Date 3/30/2022
Document Table of Contents

4.3.4. Power Analysis and Optimization

Follow the guidelines in the Power Analysis and Optimization section of the Arria® V and Cyclone® V Design Guidelines . In addition, consider the following options for the HPS portion of the device.

Processor and memory clock speeds

The biggest contribution to power consumption from the HPS is the processor clock speed and the type, size and speed of the external SDRAM program memory. Careful selection of these system parameters to satisfy the functional and performance requirements of the application helps to minimize system power consumption.

CPU Standby Modes and Dynamic Clock Gating

CPU standby modes and dynamic clock gating logic can be utilized throughout the MPU subsystem. Each CPU can be placed in standby mode, Wait for Interrupt, or Wait for Event mode to further minimize power consumption.

For more information on standby modes, refer to the Cortex®-A9 Technical Reference Manual (revision r2p0) . Power Optimization Examples are available on the Design Examples web page.

Managing Peripheral Power

When configuring the HPS component in Platform Designer (Standard), enable only those peripherals your application uses. Configure the peripherals for the lowest clock speed while maintaining functional and performance requirements. Additional power can be saved under software control by placing inactive peripherals in reset and gating off their clock sources.

Managing Power by Shutting Down Supplies

Cyclone® V SoC and Arria® V SoC support the ability to power down the FPGA portion of the device, while keeping the HPS running. Refer to the Cyclone® V SoC Smart Configuration design example on how to control the FPGA power supply regulator using the I2C connection from the HPS.